Dataflow-based reconfigurable architecture for streaming applications

A. Niedermeier; Jan Kuper; Gerardus Johannes Maria Smit

doi:10.1109/ISSoC.2012.6376365

Dataflow-based reconfigurable architecture for streaming applications

A. Niedermeier, Jan Kuper, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

12 Downloads (Pure)

Abstract

Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configuration principle of the computing cores and the behaviour of the memory blocks are based on streaming and dataflow principles. We illustrate our ideas with the implementation of a long finite impulse response (FIR) filter where memory tiles are used to store intermediate results.

Original language	Undefined
Title of host publication	Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip
Place of Publication	USA
Publisher	IEEE
Pages	1-4
Number of pages	4
ISBN (Print)	978-1-4673-2896-8
DOIs	https://doi.org/10.1109/ISSoC.2012.6376365
Publication status	Published - 10 Oct 2012
Event	Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland: Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip - USA Duration: 10 Oct 2012 → …

Publication series

Name
Publisher	IEEE Circuits & Systems Society

Conference

Conference	Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland
City	USA
Period	10/10/12 → …

Keywords

EWI-22605
METIS-296156
IR-84224

Access to Document

10.1109/ISSoC.2012.6376365

http://eprints.eemcs.utwente.nl/secure2/22605/01/06376365.pdf

Cite this

@inproceedings{6ef8cf305dcf48e9a4faad1260309390,

title = "Dataflow-based reconfigurable architecture for streaming applications",

abstract = "Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configuration principle of the computing cores and the behaviour of the memory blocks are based on streaming and dataflow principles. We illustrate our ideas with the implementation of a long finite impulse response (FIR) filter where memory tiles are used to store intermediate results.",

keywords = "EWI-22605, METIS-296156, IR-84224",

author = "A. Niedermeier and Jan Kuper and Smit, {Gerardus Johannes Maria}",

note = "10.1109/ISSoC.2012.6376365 ; Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland ; Conference date: 10-10-2012",

year = "2012",

month = oct,

day = "10",

doi = "10.1109/ISSoC.2012.6376365",

language = "Undefined",

isbn = "978-1-4673-2896-8",

publisher = "IEEE",

pages = "1--4",

booktitle = "Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip",

address = "United States",

}

Niedermeier, A, Kuper, J & Smit, GJM 2012, Dataflow-based reconfigurable architecture for streaming applications. in Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip. IEEE, USA, pp. 1-4, Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland, USA, 10/10/12. https://doi.org/10.1109/ISSoC.2012.6376365

TY - GEN

T1 - Dataflow-based reconfigurable architecture for streaming applications

AU - Niedermeier, A.

AU - Kuper, Jan

AU - Smit, Gerardus Johannes Maria

N1 - 10.1109/ISSoC.2012.6376365

PY - 2012/10/10

Y1 - 2012/10/10

N2 - Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configuration principle of the computing cores and the behaviour of the memory blocks are based on streaming and dataflow principles. We illustrate our ideas with the implementation of a long finite impulse response (FIR) filter where memory tiles are used to store intermediate results.

AB - Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configuration principle of the computing cores and the behaviour of the memory blocks are based on streaming and dataflow principles. We illustrate our ideas with the implementation of a long finite impulse response (FIR) filter where memory tiles are used to store intermediate results.

KW - EWI-22605

KW - METIS-296156

KW - IR-84224

U2 - 10.1109/ISSoC.2012.6376365

DO - 10.1109/ISSoC.2012.6376365

M3 - Conference contribution

SN - 978-1-4673-2896-8

SP - 1

EP - 4

BT - Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip

PB - IEEE

CY - USA

T2 - Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland

Y2 - 10 October 2012

ER -