Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configuration principle of the computing cores and the behaviour of the memory blocks are based on streaming and dataflow principles. We illustrate our ideas with the implementation of a long finite impulse response (FIR) filter where memory tiles are used to store intermediate results.
|Publisher||IEEE Circuits & Systems Society|
|Conference||Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland|
|Period||10/10/12 → …|