Dataflow-based reconfigurable architecture for streaming applications

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    5 Citations (Scopus)

    Abstract

    Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configuration principle of the computing cores and the behaviour of the memory blocks are based on streaming and dataflow principles. We illustrate our ideas with the implementation of a long finite impulse response (FIR) filter where memory tiles are used to store intermediate results.
    Original languageUndefined
    Title of host publicationProceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip
    Place of PublicationUSA
    PublisherIEEE Circuits & Systems Society
    Pages1-4
    Number of pages4
    ISBN (Print)978-1-4673-2896-8
    DOIs
    Publication statusPublished - 10 Oct 2012
    EventProceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland: Proceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip - USA
    Duration: 10 Oct 2012 → …

    Publication series

    Name
    PublisherIEEE Circuits & Systems Society

    Conference

    ConferenceProceedings of System on Chip (SoC), 2012 International Symposium on System-on-Chip, Tampere, Finland
    CityUSA
    Period10/10/12 → …

    Keywords

    • EWI-22605
    • METIS-296156
    • IR-84224

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