Even though superconductor electronics is capable of handling the requirements for efficient high-speed devices in telecommunication and computing, the yield is very low compared to semiconductor processes. A structured test methodology has to be developed to improve the low yield in Superconductor Electronics (SCE). We have conducted studies on a Low-Temperature Superconductor (LTS) process and have developed test structures for the detection of random defects occurring in the process. We have implemented test-routines for semi-automatic testing of processed chips for structural defects at room temperature. In this paper, we present the details of the conducted tests on those test structures and associated measurement results. One of the defects, a crack in the superconducting wire is then further analysed to study its influence on an Rapid Single Flux Quantum (RSFQ) D-type Flip-Flop.
|Publication status||Published - 2004|
|Event||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands|
Duration: 25 Nov 2004 → 26 Nov 2004
Conference number: 15
|Conference||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004|
|Period||25/11/04 → 26/11/04|