A differential pair with input transistors and provided with a variable degeneration resistor. The degeneration resistor comprises a series arrangement of two branches of coupled resistors which are shunted in mutually corresponding points by respective control transistors whose gates are interconnected. The differential pair further comprises a control loop comprising two current mirrors a bias resistor and a current source for providing a control signal to the gates of the control transistors. The control loop does not influence the DC bias of the differential pair
| Original language | Undefined |
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| Patent number | US5828265 |
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| Priority date | 9/05/96 |
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| Publication status | Published - 27 Oct 1998 |
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- METIS-118316
- EWI-27522
- IR-102630