Delay 25 an ASIC for timing adjustment in LHC

H. Furtado, J.H.R. Schrader, A. Marchioro, P. Moreira

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

    1 Citation (Scopus)
    6 Downloads (Pure)

    Abstract

    A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.
    Original languageEnglish
    Title of host publicationthe 11th Workshop on Electronics for LHC and future Experiments
    Place of PublicationGeneva
    PublisherCERN
    Pages148-152
    Number of pages5
    ISBN (Print)9290832622
    DOIs
    Publication statusPublished - Sep 2005
    Event11th Workshop on Electronics for LHC and future Experiments 2005 - Heidelberg, Germany
    Duration: 12 Sep 200516 Sep 2005

    Workshop

    Workshop11th Workshop on Electronics for LHC and future Experiments 2005
    Abbreviated titleWorkshop LHC
    Period12/09/0516/09/05

    Keywords

    • IR-67691
    • METIS-224620
    • EWI-14521

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  • Cite this

    Furtado, H., Schrader, J. H. R., Marchioro, A., & Moreira, P. (2005). Delay 25 an ASIC for timing adjustment in LHC. In the 11th Workshop on Electronics for LHC and future Experiments (pp. 148-152). Geneva: CERN. https://doi.org/10.5170/CERN-2005-011.148