Abstract
Original language | English |
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Title of host publication | the 11th Workshop on Electronics for LHC and future Experiments |
Place of Publication | Geneva |
Publisher | CERN |
Pages | 148-152 |
Number of pages | 5 |
ISBN (Print) | 9290832622 |
DOIs | |
Publication status | Published - Sep 2005 |
Event | 11th Workshop on Electronics for LHC and future Experiments 2005 - Heidelberg, Germany Duration: 12 Sep 2005 → 16 Sep 2005 |
Workshop
Workshop | 11th Workshop on Electronics for LHC and future Experiments 2005 |
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Abbreviated title | Workshop LHC |
Period | 12/09/05 → 16/09/05 |
Fingerprint
Keywords
- IR-67691
- METIS-224620
- EWI-14521
Cite this
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Delay 25 an ASIC for timing adjustment in LHC. / Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.
the 11th Workshop on Electronics for LHC and future Experiments. Geneva : CERN, 2005. p. 148-152.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic
TY - GEN
T1 - Delay 25 an ASIC for timing adjustment in LHC
AU - Furtado, H.
AU - Schrader, J.H.R.
AU - Marchioro, A.
AU - Moreira, P.
PY - 2005/9
Y1 - 2005/9
N2 - A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.
AB - A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.
KW - IR-67691
KW - METIS-224620
KW - EWI-14521
U2 - 10.5170/CERN-2005-011.148
DO - 10.5170/CERN-2005-011.148
M3 - Conference contribution
SN - 9290832622
SP - 148
EP - 152
BT - the 11th Workshop on Electronics for LHC and future Experiments
PB - CERN
CY - Geneva
ER -