Delay 25 an ASIC for timing adjustment in LHC

H. Furtado, J.H.R. Schrader, A. Marchioro, P. Moreira

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

1 Citation (Scopus)
2 Downloads (Pure)

Abstract

A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.
Original languageEnglish
Title of host publicationthe 11th Workshop on Electronics for LHC and future Experiments
Place of PublicationGeneva
PublisherCERN
Pages148-152
Number of pages5
ISBN (Print)9290832622
DOIs
Publication statusPublished - Sep 2005
Event11th Workshop on Electronics for LHC and future Experiments 2005 - Heidelberg, Germany
Duration: 12 Sep 2005 → 16 Sep 2005

Workshop

Workshop11th Workshop on Electronics for LHC and future Experiments 2005
Abbreviated titleWorkshop LHC
Period12/09/05 → 16/09/05

Fingerprint

Application specific integrated circuits
Clocks
Electric delay lines
Jitter
Calibration
Radiation
Electric potential
Temperature

Keywords

  • IR-67691
  • METIS-224620
  • EWI-14521

Cite this

Furtado, H., Schrader, J. H. R., Marchioro, A., & Moreira, P. (2005). Delay 25 an ASIC for timing adjustment in LHC. In the 11th Workshop on Electronics for LHC and future Experiments (pp. 148-152). Geneva: CERN. https://doi.org/10.5170/CERN-2005-011.148
Furtado, H. ; Schrader, J.H.R. ; Marchioro, A. ; Moreira, P. / Delay 25 an ASIC for timing adjustment in LHC. the 11th Workshop on Electronics for LHC and future Experiments. Geneva : CERN, 2005. pp. 148-152
@inproceedings{dd31f76e85ee4a718ff472c3a35630e1,
title = "Delay 25 an ASIC for timing adjustment in LHC",
abstract = "A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.",
keywords = "IR-67691, METIS-224620, EWI-14521",
author = "H. Furtado and J.H.R. Schrader and A. Marchioro and P. Moreira",
year = "2005",
month = "9",
doi = "10.5170/CERN-2005-011.148",
language = "English",
isbn = "9290832622",
pages = "148--152",
booktitle = "the 11th Workshop on Electronics for LHC and future Experiments",
publisher = "CERN",

}

Furtado, H, Schrader, JHR, Marchioro, A & Moreira, P 2005, Delay 25 an ASIC for timing adjustment in LHC. in the 11th Workshop on Electronics for LHC and future Experiments. CERN, Geneva, pp. 148-152, 11th Workshop on Electronics for LHC and future Experiments 2005, 12/09/05. https://doi.org/10.5170/CERN-2005-011.148

Delay 25 an ASIC for timing adjustment in LHC. / Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

the 11th Workshop on Electronics for LHC and future Experiments. Geneva : CERN, 2005. p. 148-152.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

TY - GEN

T1 - Delay 25 an ASIC for timing adjustment in LHC

AU - Furtado, H.

AU - Schrader, J.H.R.

AU - Marchioro, A.

AU - Moreira, P.

PY - 2005/9

Y1 - 2005/9

N2 - A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.

AB - A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from process, supply voltage and temperature variations. The phase of each channel can be independently programmed with a resolution of 0.5 ns through an I2C interface. The reference clock frequency can be 32, 40, 64 or 80 MHz. The ASIC is manufactured in a 0.25 μm CMOS technology using radiation tolerant techniques. The measured output jitter for the master channel is 19 ps (RMS) and 24 ps (RMS) for the replica channels.

KW - IR-67691

KW - METIS-224620

KW - EWI-14521

U2 - 10.5170/CERN-2005-011.148

DO - 10.5170/CERN-2005-011.148

M3 - Conference contribution

SN - 9290832622

SP - 148

EP - 152

BT - the 11th Workshop on Electronics for LHC and future Experiments

PB - CERN

CY - Geneva

ER -

Furtado H, Schrader JHR, Marchioro A, Moreira P. Delay 25 an ASIC for timing adjustment in LHC. In the 11th Workshop on Electronics for LHC and future Experiments. Geneva: CERN. 2005. p. 148-152 https://doi.org/10.5170/CERN-2005-011.148

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