Delay-fault ATPG for high-speed electrically erasable PLDs

H. Kerkhoff, M. Sachdev, C. Klaasen

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    Abstract

    A dedicated timing model has been developed for an electrically erasable PLD. The programming part, including the electrically erasable transistors, has received special attention. This timing model has been primarily developed to be used as an input for a test-pattern generator for combinational and sequential implementations especially dedicated for detecting and diagnosing small delay faults in high-speed applications.
    Original languageEnglish
    Title of host publicationProceedings of the IEEE European Test Workshop 1996
    Place of PublicationSète, France
    Pages228-232
    Publication statusPublished - 12 Jun 1996
    EventIEEE European Test Workshop, ETW 1996 - Montpellier, France
    Duration: 12 Jun 199614 Jun 1996

    Conference

    ConferenceIEEE European Test Workshop, ETW 1996
    Abbreviated titleETW
    Country/TerritoryFrance
    CityMontpellier
    Period12/06/9614/06/96

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