Delay-fault ATPG for high-speed electrically erasable PLDs

H. Kerkhoff; M. Sachdev; C. Klaasen

Delay-fault ATPG for high-speed electrically erasable PLDs

H. Kerkhoff, M. Sachdev, C. Klaasen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A dedicated timing model has been developed for an electrically erasable PLD. The programming part, including the electrically erasable transistors, has received special attention. This timing model has been primarily developed to be used as an input for a test-pattern generator for combinational and sequential implementations especially dedicated for detecting and diagnosing small delay faults in high-speed applications.

Original language	English
Title of host publication	Proceedings of the IEEE European Test Workshop 1996
Place of Publication	Sète, France
Pages	228-232
Publication status	Published - 12 Jun 1996
Event	IEEE European Test Workshop, ETW 1996 - Montpellier, France Duration: 12 Jun 1996 → 14 Jun 1996

Conference

Conference	IEEE European Test Workshop, ETW 1996
Abbreviated title	ETW
Country/Territory	France
City	Montpellier
Period	12/06/96 → 14/06/96

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@inproceedings{9933dd90f8124082b01017b377ec58df,

title = "Delay-fault ATPG for high-speed electrically erasable PLDs",

abstract = "A dedicated timing model has been developed for an electrically erasable PLD. The programming part, including the electrically erasable transistors, has received special attention. This timing model has been primarily developed to be used as an input for a test-pattern generator for combinational and sequential implementations especially dedicated for detecting and diagnosing small delay faults in high-speed applications.",

author = "H. Kerkhoff and M. Sachdev and C. Klaasen",

year = "1996",

month = jun,

day = "12",

language = "English",

pages = "228--232",

booktitle = "Proceedings of the IEEE European Test Workshop 1996",

note = "IEEE European Test Workshop, ETW 1996, ETW ; Conference date: 12-06-1996 Through 14-06-1996",

}

TY - GEN

T1 - Delay-fault ATPG for high-speed electrically erasable PLDs

AU - Kerkhoff, H.

AU - Sachdev, M.

AU - Klaasen, C.

PY - 1996/6/12

Y1 - 1996/6/12

N2 - A dedicated timing model has been developed for an electrically erasable PLD. The programming part, including the electrically erasable transistors, has received special attention. This timing model has been primarily developed to be used as an input for a test-pattern generator for combinational and sequential implementations especially dedicated for detecting and diagnosing small delay faults in high-speed applications.

AB - A dedicated timing model has been developed for an electrically erasable PLD. The programming part, including the electrically erasable transistors, has received special attention. This timing model has been primarily developed to be used as an input for a test-pattern generator for combinational and sequential implementations especially dedicated for detecting and diagnosing small delay faults in high-speed applications.

M3 - Conference contribution

SP - 228

EP - 232

BT - Proceedings of the IEEE European Test Workshop 1996

CY - Sète, France

T2 - IEEE European Test Workshop, ETW 1996

Y2 - 12 June 1996 through 14 June 1996

ER -

Delay-fault ATPG for high-speed electrically erasable PLDs

Abstract

Conference

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