Abstract
A dedicated timing model has been developed for an electrically erasable PLD. The programming part, including the electrically erasable transistors, has received special attention. This timing model has been primarily developed to be used as an input for a test-pattern generator for combinational and sequential implementations especially dedicated for detecting and diagnosing small delay faults in high-speed applications.
Original language | English |
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Title of host publication | Proceedings of the IEEE European Test Workshop 1996 |
Place of Publication | Sète, France |
Pages | 228-232 |
Publication status | Published - 12 Jun 1996 |
Event | IEEE European Test Workshop, ETW 1996 - Montpellier, France Duration: 12 Jun 1996 → 14 Jun 1996 |
Conference
Conference | IEEE European Test Workshop, ETW 1996 |
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Abbreviated title | ETW |
Country/Territory | France |
City | Montpellier |
Period | 12/06/96 → 14/06/96 |