Dependable multicore architectures at nanoscale: The view from Europe

M. Ottavi, S. Pontarelli, D. Gizopoulos, A. Paschalis, C. Bolchini, M.K. Michael, L. Anghel, M. Tahoori, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, S. Hamdioui

Research output: Contribution to journalArticleAcademicpeer-review

21 Citations (Scopus)


This article presented a survey of dependability issues faced by multi-core architectures at nanoscale technology nodes. Existing solutions against these challenges were also discussed, describing their scope of application, from technology level methodologies, to design approaches to the metrics required to evaluate the overall dependability of a system. In the future, the constant reduction of the feature size of the devices will exacerbate the issues related to aging and soft errors. This will create further challenges and at design level, an integrated design approach that will cope with the occurrence of faults at any time of their occurrence i.e., at manufacturing (thus increasing yield) and in the field (thus increasing reliability) will become more and more important to obtain economically viable and dependable systems. Dependability assessment will also need an integrated approach for cross-layer, pre- and post-silicon techniques for “just right”dependability assessment in order to avoid “overdesign”for dependability using classic guard-banding methodologies.
Original languageEnglish
Pages (from-to)17-28
JournalIEEE Design and Test
Issue number2
Publication statusPublished - 2015
Externally publishedYes


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