Stencil computations are array based algorithms that apply a computation to all array elements in a fixed regular pattern and can be found in many scientific and engineering applications. Parallelization of these applications becomes more and more important in order to keep up with the demand for computing power. FPGAs offer a lot of computing power but are considered hard to program. In this paper, a design methodology based on transformations of higher-order functions is introduced to facilitate this parallelization process. Using this methodology, efficient FPGA hardware is derived achieving good performance. Two architectures for heat flow computations are synthesized for an FPGA and evaluated. To show the general applicability of the design methodology, several applications have been implemented.
|Title of host publication||Communicating Processes Architectures 2014|
|Place of Publication||England|
|Publisher||Open Channel Publishing|
|Number of pages||14|
|Publication status||Published - Aug 2014|
|Event||Communicating Process Architectures, CPA 2014: 36th WoTUG Conference on Concurrent and Parallel Programming 2014 - University of Oxford, Oxford, United Kingdom|
Duration: 24 Aug 2014 → 27 Aug 2014
Conference number: 36
|Publisher||Open Channel publishing|
|Conference||Communicating Process Architectures, CPA 2014|
|Period||24/08/14 → 27/08/14|
- higher-order function
- space/time tradeoff
- stencil computations
Wester, R., & Kuper, J. (2014). Deriving stencil hardware accelerators from a single higher-order function. In P. H. Welch (Ed.), Communicating Processes Architectures 2014 (pp. 205-218). England: Open Channel Publishing.