Deriving stencil hardware accelerators from a single higher-order function

Rinse Wester, Jan Kuper

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    Stencil computations are array based algorithms that apply a computation to all array elements in a fixed regular pattern and can be found in many scientific and engineering applications. Parallelization of these applications becomes more and more important in order to keep up with the demand for computing power. FPGAs offer a lot of computing power but are considered hard to program. In this paper, a design methodology based on transformations of higher-order functions is introduced to facilitate this parallelization process. Using this methodology, efficient FPGA hardware is derived achieving good performance. Two architectures for heat flow computations are synthesized for an FPGA and evaluated. To show the general applicability of the design methodology, several applications have been implemented.
    Original languageUndefined
    Title of host publicationCommunicating Processes Architectures 2014
    EditorsP.H. Welch
    Place of PublicationEngland
    PublisherOpen Channel Publishing
    Number of pages14
    ISBN (Print)978-0-9565409-8-0
    Publication statusPublished - Aug 2014
    EventCommunicating Process Architectures, CPA 2014: 36th WoTUG Conference on Concurrent and Parallel Programming 2014 - University of Oxford, Oxford, United Kingdom
    Duration: 24 Aug 201427 Aug 2014
    Conference number: 36

    Publication series

    PublisherOpen Channel publishing


    ConferenceCommunicating Process Architectures, CPA 2014
    Abbreviated titleCPA
    Country/TerritoryUnited Kingdom
    Internet address


    • EWI-26124
    • higher-order function
    • space/time tradeoff
    • IR-96365
    • Haskell
    • METIS-312660
    • stencil computations

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