Design and analysis of a high-efficiencyv high-voltage class-D power output stage

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    The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.
    Original languageEnglish
    Pages (from-to)1514-1524
    Number of pages11
    JournalIEEE journal of solid-state circuits
    Issue number7
    Publication statusPublished - 1 Jul 2014


    • EWI-24886
    • IR-91436
    • METIS-305930

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