Design and analysis of a high-efficiencyv high-voltage class-D power output stage

Haifeng Ma; Ronan van der Zee; Bram Nauta

doi:10.1109/JSSC.2014.2317780

Design and analysis of a high-efficiencyv high-voltage class-D power output stage

Haifeng Ma, Ronan van der Zee, Bram Nauta

Research output: Contribution to journal › Article › Academic › peer-review

22 Citations (Scopus)

315 Downloads (Pure)

Abstract

The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.

Original language	English
Pages (from-to)	1514-1524
Number of pages	11
Journal	IEEE journal of solid-state circuits
Volume	49
Issue number	7
DOIs	https://doi.org/10.1109/JSSC.2014.2317780
Publication status	Published - 1 Jul 2014

Keywords

EWI-24886
IR-91436
METIS-305930

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Ma2014designAccepted author version, 992 KB

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Design and analysis of a high-efficiencyv high-voltage class-D power output stage

Abstract

Keywords

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