Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers

M. Ottavi; S. Pontarelli; A. Leandri; A. Salsano

doi:10.1109/DFT.2006.21

Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers

M. Ottavi, S. Pontarelli, A. Leandri, A. Salsano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

This paper investigates the effects of a class of transient faults, the so-called single event upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFT.2006.21
Publication status	Published - 2006
Externally published	Yes
Event	21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006 - Arlington, United States Duration: 4 Oct 2006 → 6 Oct 2006 Conference number: 21

Conference

Conference	21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006
Abbreviated title	DFT 2006
Country/Territory	United States
City	Arlington
Period	4/10/06 → 6/10/06

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10.1109/DFT.2006.21

Cite this

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title = "Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers",

abstract = "This paper investigates the effects of a class of transient faults, the so-called single event upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility",

author = "M. Ottavi and S. Pontarelli and A. Leandri and A. Salsano",

year = "2006",

doi = "10.1109/DFT.2006.21",

language = "English",

booktitle = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

note = "21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, DFT 2006 ; Conference date: 04-10-2006 Through 06-10-2006",

}

Ottavi, M, Pontarelli, S, Leandri, A & Salsano, A 2006, Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Arlington, Virginia, United States, 4/10/06. https://doi.org/10.1109/DFT.2006.21

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T1 - Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers

AU - Ottavi, M.

AU - Pontarelli, S.

AU - Leandri, A.

AU - Salsano, A.

N1 - Conference code: 21

PY - 2006

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N2 - This paper investigates the effects of a class of transient faults, the so-called single event upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility

AB - This paper investigates the effects of a class of transient faults, the so-called single event upsets, on the execution of programs in typical microcontroller architecture as can be found on a system on chip for embedded applications. It is observed that the consequences of targeting the registers used in the control flow can cause unexpected jumps of the program and consequent heavy effects on the results or the freeze of the microcontroller. A novel hardware based control flow checker is then introduced and implemented on an FPGA test bed together with the microcontroller core and fault injection circuitry. The FPGA implementation allows to dynamically and quickly injecting faults on the microcontroller whereas the results of the fault injection campaign allow to evaluate the fault coverage of the proposed method with a high degree of flexibility

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DO - 10.1109/DFT.2006.21

M3 - Conference contribution

BT - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

T2 - 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006

Y2 - 4 October 2006 through 6 October 2006

ER -

Design and evaluation of a hardware on-line program-flow checker for embedded microcontrollers

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