Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC

Michael Rogenmoser; Philip Wiese; Bruno Endres Forlin; Frank K. Gürkaynak; Paolo Rech; Alessandra Menicucci; Marco Ottavi; Luca Benini

doi:10.48550/arXiv.2407.05938

Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC

Michael Rogenmoser, Philip Wiese, Bruno Endres Forlin, Frank K. Gürkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini

Research output: Working paper › Preprint › Academic

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Abstract

We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteeing a device cross-section lower than $5.36 \times 10^{-12}$ cm$^2$.

Original language	English
Publisher	ArXiv.org
DOIs	https://doi.org/10.48550/arXiv.2407.05938
Publication status	Published - 8 Jul 2024

Keywords

physics.ins-det
cs.AR
hep-ex

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10.48550/arXiv.2407.05938Licence: CC BY-SA

2407.05938v1Final published version, 5.78 MBLicence: CC BY-SA

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abstract = " We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteeing a device cross-section lower than $5.36 \times 10^{-12}$ cm$^2$. ",

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AU - Rogenmoser, Michael

AU - Wiese, Philip

AU - Forlin, Bruno Endres

AU - Gürkaynak, Frank K.

AU - Rech, Paolo

AU - Menicucci, Alessandra

AU - Ottavi, Marco

AU - Benini, Luca

N1 - 4 pages (excluding title page), accepted at RADECS 2024

PY - 2024/7/8

Y1 - 2024/7/8

N2 - We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteeing a device cross-section lower than $5.36 \times 10^{-12}$ cm$^2$.

AB - We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteeing a device cross-section lower than $5.36 \times 10^{-12}$ cm$^2$.

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KW - cs.AR

KW - hep-ex

U2 - 10.48550/arXiv.2407.05938

DO - 10.48550/arXiv.2407.05938

M3 - Preprint

BT - Design and Experimental Investigation of Trikarenos

PB - ArXiv.org

ER -

Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC

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Keywords

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