Design and implementation of a hierarchical testable architecture using the boundary scan standard

R.P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg

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    Abstract

    A standardized and structured test methodology is described which is based on the boundary-scan proposal of JTAG (Joint Test Action Group). The architecture ensures the testability of the hardware from printed-circuit-board level down to integrated-circuit level. In addition, the architecture has the feature of built-in self-test at the IC level. The implementation of the architecture by means of a self-test compiler is discussed. The test hardware for the hierarchically testable architecture at the macro level consists of test interface elements and a macro test processor; these components are examined in detail
    Original languageUndefined
    Pages112-118
    DOIs
    Publication statusPublished - 1989

    Keywords

    • IR-56094

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