Design and implementation of a hierarchical testable architecture using the boundary scan standard

R.P. van Riessen; Hans G. Kerkhoff; A. Kloppenburg

doi:10.1109/ETC.1989.36231

Design and implementation of a hierarchical testable architecture using the boundary scan standard

R.P. van Riessen
, Hans G. Kerkhoff
, A. Kloppenburg

Research output: Contribution to conference › Paper

4 Citations (Scopus)

318 Downloads (Pure)

Abstract

A standardized and structured test methodology is described which is based on the boundary-scan proposal of JTAG (Joint Test Action Group). The architecture ensures the testability of the hardware from printed-circuit-board level down to integrated-circuit level. In addition, the architecture has the feature of built-in self-test at the IC level. The implementation of the architecture by means of a self-test compiler is discussed. The test hardware for the hierarchically testable architecture at the macro level consists of test interface elements and a macro test processor; these components are examined in detail

Original language	Undefined
Pages	112-118
DOIs	https://doi.org/10.1109/ETC.1989.36231
Publication status	Published - 1989
Event	1st European Test Conference, 1989 - Paris, France Duration: 12 Apr 1989 → 14 Apr 1989

Conference

Conference	1st European Test Conference, 1989
Period	12/04/89 → 14/04/89
Other	12-14 April 1989

Keywords

IR-56094

Access to Document

10.1109/ETC.1989.36231

00036231

Cite this

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title = "Design and implementation of a hierarchical testable architecture using the boundary scan standard",

abstract = "A standardized and structured test methodology is described which is based on the boundary-scan proposal of JTAG (Joint Test Action Group). The architecture ensures the testability of the hardware from printed-circuit-board level down to integrated-circuit level. In addition, the architecture has the feature of built-in self-test at the IC level. The implementation of the architecture by means of a self-test compiler is discussed. The test hardware for the hierarchically testable architecture at the macro level consists of test interface elements and a macro test processor; these components are examined in detail",

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U2 - 10.1109/ETC.1989.36231

DO - 10.1109/ETC.1989.36231

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