Design and Implementation of a linear-phase equalizer in digital audio signal processing

C.H. Slump; C.G.M. van Asma; J.K.P. Barels; W.J.A Brunink; F.B. Drenth; J.V. Pol; D.S. Schouten; M.M. Samsom; O.E. Herrmann

doi:10.1109/VLSISP.1992.641062

Design and Implementation of a linear-phase equalizer in digital audio signal processing

C.H. Slump, C.G.M. van Asma, J.K.P. Barels, W.J.A Brunink, F.B. Drenth, J.V. Pol, D.S. Schouten, M.M. Samsom, O.E. Herrmann

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

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Abstract

This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the signal processing algorithms constituting the global design of the equalizer are computer simulated. The third step includes the realization of the equalizer design using one or more programmable DSP¿s. In order to minimize the number of DSP chips necessary for the realization, this step requires the optimization of the structure and mapping of the algorithm on the resources of the DSP. The number of processor cycles is crucial in this optimization. The purpose of the resulting prototype is to test and to validate in a digital audio environment the specification generated in the first step. The programmability of the DSP¿s allows for specification changes at this stage of the project. The fourth step is the VLSI implementatin of the validated algorithm of the previous phase. For this purpose the structure of the algorithm is optimized in order to take full advantage of the silicon resources. Speed and required area are the crucial parameters in this optimization. The final step includes the testing of the completed chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will emphasize the algorithmic and design considerations together with the results.

Original language	English
Title of host publication	Workshop on VLSI Signal Processing
Subtitle of host publication	28-30 October 1992, Los Angeles, CA, USA
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	297-306
Number of pages	12
ISBN (Print)	0-7803-0811-5
DOIs	https://doi.org/10.1109/VLSISP.1992.641062
Publication status	Published - 28 Oct 1992
Event	Workshop on VLSI Signal Processing V - Los Angeles, United States Duration: 28 Oct 1992 → 30 Oct 1992

Workshop

Workshop	Workshop on VLSI Signal Processing V
Country/Territory	United States
City	Los Angeles
Period	28/10/92 → 30/10/92

Access to Document

10.1109/VLSISP.1992.641062

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Cite this

Slump, C. H., van Asma, C. G. M., Barels, J. K. P., Brunink, W. J. A., Drenth, F. B., Pol, J. V., Schouten, D. S., Samsom, M. M., & Herrmann, O. E. (1992). Design and Implementation of a linear-phase equalizer in digital audio signal processing. In Workshop on VLSI Signal Processing: 28-30 October 1992, Los Angeles, CA, USA (pp. 297-306). IEEE. https://doi.org/10.1109/VLSISP.1992.641062

@inproceedings{cb72a2524c8c4a529bf438d7bcd091db,

title = "Design and Implementation of a linear-phase equalizer in digital audio signal processing",

abstract = "This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the signal processing algorithms constituting the global design of the equalizer are computer simulated. The third step includes the realization of the equalizer design using one or more programmable DSP¿s. In order to minimize the number of DSP chips necessary for the realization, this step requires the optimization of the structure and mapping of the algorithm on the resources of the DSP. The number of processor cycles is crucial in this optimization. The purpose of the resulting prototype is to test and to validate in a digital audio environment the specification generated in the first step. The programmability of the DSP¿s allows for specification changes at this stage of the project. The fourth step is the VLSI implementatin of the validated algorithm of the previous phase. For this purpose the structure of the algorithm is optimized in order to take full advantage of the silicon resources. Speed and required area are the crucial parameters in this optimization. The final step includes the testing of the completed chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will emphasize the algorithmic and design considerations together with the results.",

author = "C.H. Slump and {van Asma}, C.G.M. and J.K.P. Barels and W.J.A Brunink and F.B. Drenth and J.V. Pol and D.S. Schouten and M.M. Samsom and O.E. Herrmann",

year = "1992",

month = oct,

day = "28",

doi = "10.1109/VLSISP.1992.641062",

language = "English",

isbn = "0-7803-0811-5",

pages = "297--306",

booktitle = "Workshop on VLSI Signal Processing",

publisher = "IEEE",

address = "United States",

note = "Workshop on VLSI Signal Processing V ; Conference date: 28-10-1992 Through 30-10-1992",

}

Slump, CH, van Asma, CGM, Barels, JKP, Brunink, WJA, Drenth, FB, Pol, JV, Schouten, DS, Samsom, MM & Herrmann, OE 1992, Design and Implementation of a linear-phase equalizer in digital audio signal processing. in Workshop on VLSI Signal Processing: 28-30 October 1992, Los Angeles, CA, USA. IEEE, Piscataway, NJ, pp. 297-306, Workshop on VLSI Signal Processing V, Los Angeles, United States, 28/10/92. https://doi.org/10.1109/VLSISP.1992.641062

Design and Implementation of a linear-phase equalizer in digital audio signal processing. / Slump, C.H.; van Asma, C.G.M.; Barels, J.K.P. et al.
Workshop on VLSI Signal Processing: 28-30 October 1992, Los Angeles, CA, USA. Piscataway, NJ: IEEE, 1992. p. 297-306.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Design and Implementation of a linear-phase equalizer in digital audio signal processing

AU - Slump, C.H.

AU - van Asma, C.G.M.

AU - Barels, J.K.P.

AU - Brunink, W.J.A

AU - Drenth, F.B.

AU - Pol, J.V.

AU - Schouten, D.S.

AU - Samsom, M.M.

AU - Herrmann, O.E.

PY - 1992/10/28

Y1 - 1992/10/28

N2 - This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the signal processing algorithms constituting the global design of the equalizer are computer simulated. The third step includes the realization of the equalizer design using one or more programmable DSP¿s. In order to minimize the number of DSP chips necessary for the realization, this step requires the optimization of the structure and mapping of the algorithm on the resources of the DSP. The number of processor cycles is crucial in this optimization. The purpose of the resulting prototype is to test and to validate in a digital audio environment the specification generated in the first step. The programmability of the DSP¿s allows for specification changes at this stage of the project. The fourth step is the VLSI implementatin of the validated algorithm of the previous phase. For this purpose the structure of the algorithm is optimized in order to take full advantage of the silicon resources. Speed and required area are the crucial parameters in this optimization. The final step includes the testing of the completed chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will emphasize the algorithmic and design considerations together with the results.

AB - This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the signal processing algorithms constituting the global design of the equalizer are computer simulated. The third step includes the realization of the equalizer design using one or more programmable DSP¿s. In order to minimize the number of DSP chips necessary for the realization, this step requires the optimization of the structure and mapping of the algorithm on the resources of the DSP. The number of processor cycles is crucial in this optimization. The purpose of the resulting prototype is to test and to validate in a digital audio environment the specification generated in the first step. The programmability of the DSP¿s allows for specification changes at this stage of the project. The fourth step is the VLSI implementatin of the validated algorithm of the previous phase. For this purpose the structure of the algorithm is optimized in order to take full advantage of the silicon resources. Speed and required area are the crucial parameters in this optimization. The final step includes the testing of the completed chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will emphasize the algorithmic and design considerations together with the results.

U2 - 10.1109/VLSISP.1992.641062

DO - 10.1109/VLSISP.1992.641062

M3 - Conference contribution

SN - 0-7803-0811-5

SP - 297

EP - 306

BT - Workshop on VLSI Signal Processing

PB - IEEE

CY - Piscataway, NJ

T2 - Workshop on VLSI Signal Processing V

Y2 - 28 October 1992 through 30 October 1992

ER -

Design and Implementation of a linear-phase equalizer in digital audio signal processing

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Workshop

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