Design and Implementation of a linear-phase equalizer in digital audio signal processing

Cornelis H. Slump, C.G.M. van Asma, J.K.P. Barels, J.K.P. Barels, W.J.A Brunink, F.B. Drenth, J.V. Pol, D.S. Schouten, M.M. Samsom, M.M. Samsom, O.E. Herrmann

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    3 Citations (Scopus)
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    This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the signal processing algorithms constituting the global design of the equalizer are computer simulated. The third step includes the realization of the equalizer design using one or more programmable DSP¿s. In order to minimize the number of DSP chips necessary for the realization, this step requires the optimization of the structure and mapping of the algorithm on the resources of the DSP. The number of processor cycles is crucial in this optimization. The purpose of the resulting prototype is to test and to validate in a digital audio environment the specification generated in the first step. The programmability of the DSP¿s allows for specification changes at this stage of the project. The fourth step is the VLSI implementatin of the validated algorithm of the previous phase. For this purpose the structure of the algorithm is optimized in order to take full advantage of the silicon resources. Speed and required area are the crucial parameters in this optimization. The final step includes the testing of the completed chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will emphasize the algorithmic and design considerations together with the results.
    Original languageUndefined
    Title of host publicationVLSI Signal Processing, IEEE Signal Processing Society Workshop on VLSI Signal Processing
    Place of PublicationNapa Valley, Napa, California, USA
    Number of pages12
    ISBN (Print)0-7803-0811-5
    Publication statusPublished - 28 Oct 1992
    EventWorkshop on VLSI Signal Processing V - Napa Valley, CA, USA
    Duration: 28 Oct 199230 Oct 1992

    Publication series



    WorkshopWorkshop on VLSI Signal Processing V
    Other28-30 October 1992


    • METIS-113119
    • IR-16234

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