Design and Test Space Exploration of Transport-Triggered Architectures

V. Zivkovic; R.J.W.T. Tangelder; Hans G. Kerkhoff

doi:10.1109/DATE.2000.840031

Design and Test Space Exploration of Transport-Triggered Architectures

V. Zivkovic, R.J.W.T. Tangelder, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

185 Downloads (Pure)

Abstract

This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ¿MOVE¿ framework has been addressed. The approach is validated with respect to the ¿Crypt¿ Unix application

Original language	Undefined
Title of host publication	Design, Automation and Test in Europe
Place of Publication	Paris, France
Publisher	IEEE
Pages	146-151
Number of pages	6
DOIs	https://doi.org/10.1109/DATE.2000.840031
Publication status	Published - 27 Mar 2000
Event	2000 Design, Automation & Test in Europe Conference & Exhibition, DATE 2000 - Paris, France Duration: 27 Mar 2000 → 30 Mar 2000

Publication series

Name
Publisher	IEEE

Conference

Conference	2000 Design, Automation & Test in Europe Conference & Exhibition, DATE 2000
Abbreviated title	DATE
Country/Territory	France
City	Paris
Period	27/03/00 → 30/03/00

Keywords

IR-16128
METIS-113013

Access to Document

10.1109/DATE.2000.840031

00840031

Cite this

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title = "Design and Test Space Exploration of Transport-Triggered Architectures",

abstract = "This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ¿MOVE¿ framework has been addressed. The approach is validated with respect to the ¿Crypt¿ Unix application",

keywords = "IR-16128, METIS-113013",

author = "V. Zivkovic and R.J.W.T. Tangelder and Kerkhoff, {Hans G.}",

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AU - Zivkovic, V.

AU - Tangelder, R.J.W.T.

AU - Kerkhoff, Hans G.

PY - 2000/3/27

Y1 - 2000/3/27

N2 - This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ¿MOVE¿ framework has been addressed. The approach is validated with respect to the ¿Crypt¿ Unix application

AB - This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ¿MOVE¿ framework has been addressed. The approach is validated with respect to the ¿Crypt¿ Unix application

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KW - METIS-113013

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DO - 10.1109/DATE.2000.840031

M3 - Conference contribution

SP - 146

EP - 151

BT - Design, Automation and Test in Europe

PB - IEEE

CY - Paris, France

T2 - 2000 Design, Automation & Test in Europe Conference & Exhibition, DATE 2000

Y2 - 27 March 2000 through 30 March 2000

ER -