Design and Test Space Exploration of Transport-Triggered Architectures

V. Zivkovic, R.J.W.T. Tangelder, Hans G. Kerkhoff

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    Abstract

    This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ¿MOVE¿ framework has been addressed. The approach is validated with respect to the ¿Crypt¿ Unix application
    Original languageUndefined
    Title of host publicationDesign, Automation and Test in Europe
    Place of PublicationParis, France
    PublisherIEEE
    Pages146-151
    Number of pages6
    DOIs
    Publication statusPublished - 27 Mar 2000

    Publication series

    Name
    PublisherIEEE

    Keywords

    • IR-16128
    • METIS-113013

    Cite this

    Zivkovic, V., Tangelder, R. J. W. T., & Kerkhoff, H. G. (2000). Design and Test Space Exploration of Transport-Triggered Architectures. In Design, Automation and Test in Europe (pp. 146-151). Paris, France: IEEE. https://doi.org/10.1109/DATE.2000.840031