Design Considerations for Integrated High-Frequency p-Channel JFET's

To achieve high-frequency performance of integrated p- channel JFET’s, the large substrate capacitance is decoupled by separating the top gate from the bottom gate. Further optimization of the JFET design, with respect to frequency response, is studied here both theoretically and experimentally using devices produced in a double-implantation BIFET process for analog integrated circuits. Results show that attentuation of the hole mobility due to high doping level effects make it favorable to design with wide lightly doped channels. To avoid undesirable currents from the source to the drain or from the top to the bottom gate, the channel must be uniform. This and the requirements for high-frequency performance put additional demands on the technology. Use of the separated-gate JFET in circuit designs is complicated by the presence of a large bulk effect and the top-gate to bottom-gate reachthrough diode.