Design for Delay Testability in High-Speed Digital ICs

Hans G. Kerkhoff, H. Speek, M Sashani, M. Sachdev

    Research output: Contribution to journalArticleAcademicpeer-review

    2 Citations (Scopus)
    Original languageUndefined
    Pages (from-to)225-232
    Number of pages8
    JournalJournal of electronic testing
    Volume17
    Issue number3
    Publication statusPublished - 2001

    Keywords

    • METIS-201757

    Cite this

    Kerkhoff, H. G., Speek, H., Sashani, M., & Sachdev, M. (2001). Design for Delay Testability in High-Speed Digital ICs. Journal of electronic testing, 17(3), 225-232.