Design-for-Delay Testability Techniques for High-Speed Digital Circuits

H.J. Vermaak

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    47 Downloads (Pure)

    Abstract

    The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays’ circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is getting more and more important
    Original languageEnglish
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Kerkhoff, Hans Gerard, Advisor
    • Krol, Th., Supervisor
    • Jordaan, G.D., Supervisor, External person
    Thesis sponsors
    Award date7 Dec 2005
    Place of PublicationEnschede
    Publisher
    Print ISBNs90-365-2259-5
    Publication statusPublished - 7 Dec 2005

    Keywords

    • METIS-226912
    • EWI-20043
    • IR-57440

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