Design-for-Delay Testability Techniques for High-Speed Digital Circuits

H.J. Vermaak

Design-for-Delay Testability Techniques for High-Speed Digital Circuits

H.J. Vermaak

Research output: Thesis › PhD Thesis - Research UT, graduation UT

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Abstract

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays’ circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is getting more and more important

Original language	English
Awarding Institution	University of Twente
Supervisors/Advisors	Kerkhoff, Hans G., Advisor Krol, Th., Supervisor Jordaan, G.D., Supervisor, External person
Thesis sponsors	Nationale Onderzoek Stichting vanZuid Afrika (NRF)
Award date	7 Dec 2005
Place of Publication	Enschede
Publisher	University of Twente
Print ISBNs	90-365-2259-5
Publication status	Published - 7 Dec 2005

Keywords

METIS-226912
EWI-20043
IR-57440

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title = "Design-for-Delay Testability Techniques for High-Speed Digital Circuits",

abstract = "The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays{\textquoteright} circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is getting more and more important",

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AU - Vermaak, H.J.

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N2 - The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays’ circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is getting more and more important

AB - The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays’ circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is getting more and more important

KW - METIS-226912

KW - EWI-20043

KW - IR-57440

M3 - PhD Thesis - Research UT, graduation UT

SN - 90-365-2259-5

PB - University of Twente

CY - Enschede

ER -

Design-for-Delay Testability Techniques for High-Speed Digital Circuits

Abstract

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