Design of a 1-chip IBM-3270 protocol handler

L. Spaanenburg

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    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4 manweeks. The design methodology stresses the application of high-level silicon constructs and built-in testability.
    Original languageUndefined
    Pages (from-to)189-194
    JournalMicroprocessing and Microprogramming
    Issue number1-5
    Publication statusPublished - 1989


    • built-in testability
    • logic-enhanced memory
    • VLSI design
    • microarchitecture
    • IR-70581
    • ASIC

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