Design of a Highly Dependable Beamforming Chip

Hans G. Kerkhoff

doi:10.1109/DSD.2009.152

Design of a Highly Dependable Beamforming Chip

Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

244 Downloads (Pure)

Abstract

As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.

Original language	Undefined
Title of host publication	Proceedings of Euromicro on Digital System Design (DSD09)
Editors	Xiao Zhang, X. Zhang
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE
Pages	729-735
Number of pages	7
ISBN (Print)	978-0-7695-3782-5
DOIs	https://doi.org/10.1109/DSD.2009.152
Publication status	Published - Aug 2009
Event	12th EUROMICRO Conference on Digital System Design, DSD 2009: Architectures, Methods and Tools - Conference and Cultural Centre of the University of Patras, Patras, Greece Duration: 27 Aug 2009 → 29 Aug 2009 Conference number: 12 http://www.iuma.ulpgc.es/dsd09/

Publication series

Name
Publisher	IEEE Computer Society Press

Conference

Conference	12th EUROMICRO Conference on Digital System Design, DSD 2009
Abbreviated title	DSD
Country/Territory	Greece
City	Patras
Period	27/08/09 → 29/08/09
Internet address	http://www.iuma.ulpgc.es/dsd09/

Keywords

IR-69091
EWI-16913
EC Grant Agreement nr.: FP7/215881
METIS-264189

Access to Document

10.1109/DSD.2009.152

Cite this

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title = "Design of a Highly Dependable Beamforming Chip",

abstract = "As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.",

keywords = "IR-69091, EWI-16913, EC Grant Agreement nr.: FP7/215881, METIS-264189",

author = "Kerkhoff, {Hans G.}",

note = "10.1109/DSD.2009.152 ; 12th EUROMICRO Conference on Digital System Design, DSD 2009 ; Conference date: 27-08-2009 Through 29-08-2009",

year = "2009",

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doi = "10.1109/DSD.2009.152",

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isbn = "978-0-7695-3782-5",

publisher = "IEEE",

pages = "729--735",

editor = "Xiao Zhang and X. Zhang",

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AB - As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.

KW - IR-69091

KW - EWI-16913

KW - EC Grant Agreement nr.: FP7/215881

KW - METIS-264189

U2 - 10.1109/DSD.2009.152

DO - 10.1109/DSD.2009.152

M3 - Conference contribution

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