Design of a Highly Dependable Beamforming Chip

Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    9 Citations (Scopus)
    245 Downloads (Pure)


    As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out following the IEC standard 62347. To meet the dependability requirements, a dedicated infrastructural IP (IIP) and supporting software and hardware have been designed and included as part of the dependability infrastructure of the chip. This IIP can periodically verify the correctness of the tile processors and coordinate the run-time mapping reconfiguration software to isolate the faulty tiles at run time and assign spare processors for the open DSP tasks. Dependability graphs show a significant improvement of the application chip incorporating the design-for-dependability hardware and software.
    Original languageUndefined
    Title of host publicationProceedings of Euromicro on Digital System Design (DSD09)
    EditorsXiao Zhang, X. Zhang
    Place of PublicationLos Alamitos, CA, USA
    Number of pages7
    ISBN (Print)978-0-7695-3782-5
    Publication statusPublished - Aug 2009
    Event12th EUROMICRO Conference on Digital System Design, DSD 2009: Architectures, Methods and Tools - Conference and Cultural Centre of the University of Patras, Patras, Greece
    Duration: 27 Aug 200929 Aug 2009
    Conference number: 12

    Publication series

    PublisherIEEE Computer Society Press


    Conference12th EUROMICRO Conference on Digital System Design, DSD 2009
    Abbreviated titleDSD
    Internet address


    • IR-69091
    • EWI-16913
    • EC Grant Agreement nr.: FP7/215881
    • METIS-264189

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