Design of a QCA memory with parallel read/serial write

M. Ottavi; V. Vankamamidi; F. Lombardi; S. Pontarelli; A. Salsano

doi:10.1109/ISVLSI.2005.27

Design of a QCA memory with parallel read/serial write

M. Ottavi, V. Vankamamidi, F. Lombardi, S. Pontarelli, A. Salsano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

22 Citations (Scopus)

Abstract

This paper presents a novel memory architecture for implementation by quantum-dot cellular automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
DOIs	https://doi.org/10.1109/ISVLSI.2005.27
Publication status	Published - 2005
Externally published	Yes
Event	IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2005: New Frontiers in VLSI Design - Tampa, United States Duration: 11 May 2005 → 12 May 2005

Conference

Conference	IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2005
Abbreviated title	ISVLSI 2005
Country/Territory	United States
City	Tampa
Period	11/05/05 → 12/05/05

Access to Document

10.1109/ISVLSI.2005.27

Cite this

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title = "Design of a QCA memory with parallel read/serial write",

abstract = "This paper presents a novel memory architecture for implementation by quantum-dot cellular automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.",

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year = "2005",

doi = "10.1109/ISVLSI.2005.27",

language = "English",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI",

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T1 - Design of a QCA memory with parallel read/serial write

AU - Ottavi, M.

AU - Vankamamidi, V.

AU - Lombardi, F.

AU - Pontarelli, S.

AU - Salsano, A.

PY - 2005

Y1 - 2005

N2 - This paper presents a novel memory architecture for implementation by quantum-dot cellular automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.

AB - This paper presents a novel memory architecture for implementation by quantum-dot cellular automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.

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U2 - 10.1109/ISVLSI.2005.27

DO - 10.1109/ISVLSI.2005.27

M3 - Conference contribution

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

T2 - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2005

Y2 - 11 May 2005 through 12 May 2005

ER -

Design of a QCA memory with parallel read/serial write

Abstract

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