Design of a totally self checking signature analysis checker for finite state machines

M. Ottavi; G.C. Cardarilli; D. Cellitti; S. Pontarelli; M. Re; A. Salsano

doi:10.1109/DFTVS.2001.966794

Design of a totally self checking signature analysis checker for finite state machines

M. Ottavi, G.C. Cardarilli, D. Cellitti, S. Pontarelli, M. Re, A. Salsano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.

Original language	English
Title of host publication	IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFTVS.2001.966794
Publication status	Published - 2001
Externally published	Yes
Event	IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2001 - San Francisco, United States Duration: 24 Oct 2001 → 26 Oct 2001

Conference

Conference	IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2001
Country/Territory	United States
City	San Francisco
Period	24/10/01 → 26/10/01

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10.1109/DFTVS.2001.966794

Cite this

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title = "Design of a totally self checking signature analysis checker for finite state machines",

abstract = "This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.",

author = "M. Ottavi and G.C. Cardarilli and D. Cellitti and S. Pontarelli and M. Re and A. Salsano",

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language = "English",

isbn = "0-7695-1203-8",

booktitle = "IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems",

note = "IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2001 ; Conference date: 24-10-2001 Through 26-10-2001",

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Ottavi, M, Cardarilli, GC, Cellitti, D, Pontarelli, S, Re, M & Salsano, A 2001, Design of a totally self checking signature analysis checker for finite state machines. in IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2001, San Francisco, California, United States, 24/10/01. https://doi.org/10.1109/DFTVS.2001.966794

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AU - Cardarilli, G.C.

AU - Cellitti, D.

AU - Pontarelli, S.

AU - Re, M.

AU - Salsano, A.

PY - 2001

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N2 - This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.

AB - This paper describes the design of a totally self-checking signature analysis checker to be used to implement self-checking finite state machines. The application of the signature analysis method is studied taking into account trade off criteria concerning area and timing constraints requested in specific applications. In this paper, we propose a novel VHDL realization of this methodology suitable for the implementation of the SSMM for satellite applications. Finally, we present a general criterion to evaluate the optimal solution in terms of area overhead between the proposed method and a typical duplication and compare strategy.

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U2 - 10.1109/DFTVS.2001.966794

DO - 10.1109/DFTVS.2001.966794

M3 - Conference contribution

SN - 0-7695-1203-8

BT - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

T2 - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2001

Y2 - 24 October 2001 through 26 October 2001

ER -

Design of a totally self checking signature analysis checker for finite state machines

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