Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor

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    Abstract

    Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential dependability issues. Several additional innovative approaches with regard to dependability have been incorporated, like the NoC, wrapper and Network Interface design. The Dependability Manager design has been verified on an FPGA and is being processed in UMC CMOS technology as part of a many-core processor.
    Original languageUndefined
    Title of host publicationFifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010
    Place of PublicationLos Alamitos, CA
    PublisherIEEE Computer Society
    Pages270-275
    Number of pages6
    ISBN (Print)978-0-7695-3978-2
    DOIs
    Publication statusPublished - 13 Jan 2010
    EventFifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010 - Ho Chi Minh City, Vietnam
    Duration: 13 Jan 201015 Jan 2010

    Publication series

    Name
    PublisherIEEE Computer Society Press

    Conference

    ConferenceFifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010
    Period13/01/1015/01/10
    Other13-15 January 2010

    Keywords

    • METIS-276006
    • BIST
    • Availability
    • IR-75307
    • SoC
    • EWI-17253
    • Reconfiguration
    • DfX
    • Dependability
    • EC Grant Agreement nr.: FP7/215881
    • many-core processors
    • Reliability

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