Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor

Hans G. Kerkhoff; Xiao Zhang

doi:10.1109/DELTA.2010.57

Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor

Hans G. Kerkhoff, Xiao Zhang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

13 Citations (Scopus)

133 Downloads (Pure)

Abstract

Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential dependability issues. Several additional innovative approaches with regard to dependability have been incorporated, like the NoC, wrapper and Network Interface design. The Dependability Manager design has been verified on an FPGA and is being processed in UMC CMOS technology as part of a many-core processor.

Original language	English
Title of host publication	Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010
Place of Publication	Los Alamitos, CA
Publisher	IEEE
Pages	270-275
Number of pages	6
ISBN (Print)	978-0-7695-3978-2
DOIs	https://doi.org/10.1109/DELTA.2010.57
Publication status	Published - 13 Jan 2010
Event	5th IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010 - Ho Chi Minh City, Viet Nam Duration: 13 Jan 2010 → 15 Jan 2010

Conference

Conference	5th IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010
Country/Territory	Viet Nam
City	Ho Chi Minh City
Period	13/01/10 → 15/01/10

Keywords

BIST
Availability
SoC
Reconfiguration
DfX
Dependability
EC Grant Agreement nr.: FP7/215881
many-core processors
Reliability

Access to Document

10.1109/DELTA.2010.57

Kerkhoff2010designAccepted author version, 1.01 MB

Cite this

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title = "Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor",

abstract = "Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential dependability issues. Several additional innovative approaches with regard to dependability have been incorporated, like the NoC, wrapper and Network Interface design. The Dependability Manager design has been verified on an FPGA and is being processed in UMC CMOS technology as part of a many-core processor.",

keywords = "BIST, Availability, SoC, Reconfiguration, DfX, Dependability, EC Grant Agreement nr.: FP7/215881, many-core processors, Reliability",

author = "Kerkhoff, {Hans G.} and Xiao Zhang",

year = "2010",

month = jan,

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doi = "10.1109/DELTA.2010.57",

language = "English",

isbn = "978-0-7695-3978-2",

pages = "270--275",

booktitle = "Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010",

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note = "5th IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010 ; Conference date: 13-01-2010 Through 15-01-2010",

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Kerkhoff, HG & Zhang, X 2010, Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor. in Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010. IEEE, Los Alamitos, CA, pp. 270-275, 5th IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Viet Nam, 13/01/10. https://doi.org/10.1109/DELTA.2010.57

Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor. / Kerkhoff, Hans G.; Zhang, Xiao.
Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010. Los Alamitos, CA: IEEE, 2010. p. 270-275.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential dependability issues. Several additional innovative approaches with regard to dependability have been incorporated, like the NoC, wrapper and Network Interface design. The Dependability Manager design has been verified on an FPGA and is being processed in UMC CMOS technology as part of a many-core processor.

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KW - SoC

KW - Reconfiguration

KW - DfX

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KW - Reliability

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T2 - 5th IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010

Y2 - 13 January 2010 through 15 January 2010

ER -

Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor

Abstract

Conference

Keywords

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