Design of MoS2based Inverter Circuits considering Interface Trap effect

S. Sarath; Darshni Manekar; Rajendra P. Shukla; Chandan Yadav

doi:10.1109/VLSID60093.2024.00012

Design of MoS₂based Inverter Circuits considering Interface Trap effect

S. Sarath^*, Darshni Manekar, Rajendra P. Shukla, Chandan Yadav

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

This work presents a comprehensive study on designing MoS2 field-effect-transistor (FET) based inverter circuits accounting for the interface trap effect in the transistors. To perform the presented work, a compact model is developed considering interface traps, implemented in Verilog-A, and validated against experimental data of MoS2 based FETs. The compact model implemented in Verilog-A and extracted model parameters using IC-CAP are further used in the CAD tool Cadence® Virtuoso to perform circuit design and simulation analysis. The inverter circuit design and analysis in Cadence® Virtuoso shows that interface traps in both driver and load transistors can impact the inverter's static and dynamic behavior. The impact of interface traps in driver and load transistors on inverter performance are different. An increasing impact on inverter performance is visible with increasing interface traps. The inverter's static and dynamic behavior considered in the study are voltage transfer characteristics, gain, noise margin, delay, power, and power delay product.

Original language	English
Title of host publication	Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	43-48
Number of pages	6
ISBN (Electronic)	9798350384406
DOIs	https://doi.org/10.1109/VLSID60093.2024.00012
Publication status	Published - 2 Apr 2024
Event	37th International Conference on VLSI Design, VLSID 2024 - Kolkata, West Bengal, India Duration: 6 Jan 2024 → 10 Jan 2024 Conference number: 37

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Conference

Conference	37th International Conference on VLSI Design, VLSID 2024
Abbreviated title	VLSID 2024
Country/Territory	India
City	Kolkata, West Bengal
Period	6/01/24 → 10/01/24

Keywords

n/a OA procedure
Interface Trap
Inverter
MoS FET
Verilog-A
Compact model

Access to Document

10.1109/VLSID60093.2024.00012

Cite this

Sarath, S., Manekar, D., Shukla, R. P., & Yadav, C. (2024). Design of MoS₂based Inverter Circuits considering Interface Trap effect. In Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024 (pp. 43-48). (Proceedings of the IEEE International Conference on VLSI Design). IEEE. https://doi.org/10.1109/VLSID60093.2024.00012

Sarath, S. ; Manekar, Darshni ; Shukla, Rajendra P. et al. / Design of MoS₂based Inverter Circuits considering Interface Trap effect. Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. Piscataway, NJ : IEEE, 2024. pp. 43-48 (Proceedings of the IEEE International Conference on VLSI Design).

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abstract = "This work presents a comprehensive study on designing MoS2 field-effect-transistor (FET) based inverter circuits accounting for the interface trap effect in the transistors. To perform the presented work, a compact model is developed considering interface traps, implemented in Verilog-A, and validated against experimental data of MoS2 based FETs. The compact model implemented in Verilog-A and extracted model parameters using IC-CAP are further used in the CAD tool Cadence{\textregistered} Virtuoso to perform circuit design and simulation analysis. The inverter circuit design and analysis in Cadence{\textregistered} Virtuoso shows that interface traps in both driver and load transistors can impact the inverter's static and dynamic behavior. The impact of interface traps in driver and load transistors on inverter performance are different. An increasing impact on inverter performance is visible with increasing interface traps. The inverter's static and dynamic behavior considered in the study are voltage transfer characteristics, gain, noise margin, delay, power, and power delay product.",

keywords = "n/a OA procedure, Interface Trap, Inverter, MoS FET, Verilog-A, Compact model",

author = "S. Sarath and Darshni Manekar and Shukla, {Rajendra P.} and Chandan Yadav",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 37th International Conference on VLSI Design, VLSID 2024, VLSID 2024 ; Conference date: 06-01-2024 Through 10-01-2024",

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Sarath, S, Manekar, D, Shukla, RP & Yadav, C 2024, Design of MoS₂based Inverter Circuits considering Interface Trap effect. in Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. Proceedings of the IEEE International Conference on VLSI Design, IEEE, Piscataway, NJ, pp. 43-48, 37th International Conference on VLSI Design, VLSID 2024, Kolkata, West Bengal, India, 6/01/24. https://doi.org/10.1109/VLSID60093.2024.00012

Design of MoS₂based Inverter Circuits considering Interface Trap effect. / Sarath, S.; Manekar, Darshni; Shukla, Rajendra P. et al.
Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. Piscataway, NJ: IEEE, 2024. p. 43-48 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Manekar, Darshni

AU - Shukla, Rajendra P.

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N2 - This work presents a comprehensive study on designing MoS2 field-effect-transistor (FET) based inverter circuits accounting for the interface trap effect in the transistors. To perform the presented work, a compact model is developed considering interface traps, implemented in Verilog-A, and validated against experimental data of MoS2 based FETs. The compact model implemented in Verilog-A and extracted model parameters using IC-CAP are further used in the CAD tool Cadence® Virtuoso to perform circuit design and simulation analysis. The inverter circuit design and analysis in Cadence® Virtuoso shows that interface traps in both driver and load transistors can impact the inverter's static and dynamic behavior. The impact of interface traps in driver and load transistors on inverter performance are different. An increasing impact on inverter performance is visible with increasing interface traps. The inverter's static and dynamic behavior considered in the study are voltage transfer characteristics, gain, noise margin, delay, power, and power delay product.

AB - This work presents a comprehensive study on designing MoS2 field-effect-transistor (FET) based inverter circuits accounting for the interface trap effect in the transistors. To perform the presented work, a compact model is developed considering interface traps, implemented in Verilog-A, and validated against experimental data of MoS2 based FETs. The compact model implemented in Verilog-A and extracted model parameters using IC-CAP are further used in the CAD tool Cadence® Virtuoso to perform circuit design and simulation analysis. The inverter circuit design and analysis in Cadence® Virtuoso shows that interface traps in both driver and load transistors can impact the inverter's static and dynamic behavior. The impact of interface traps in driver and load transistors on inverter performance are different. An increasing impact on inverter performance is visible with increasing interface traps. The inverter's static and dynamic behavior considered in the study are voltage transfer characteristics, gain, noise margin, delay, power, and power delay product.

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PB - IEEE

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Y2 - 6 January 2024 through 10 January 2024

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Sarath S, Manekar D, Shukla RP, Yadav C. Design of MoS₂based Inverter Circuits considering Interface Trap effect. In Proceedings - 37th International Conference on VLSI Design, VLSID 2024 - held concurrently with 23rd International Conference on Embedded Systems, ES 2024. Piscataway, NJ: IEEE. 2024. p. 43-48. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSID60093.2024.00012