Design of MoS₂based Inverter Circuits considering Interface Trap effect

This work presents a comprehensive study on designing MoS2 field-effect-transistor (FET) based inverter circuits accounting for the interface trap effect in the transistors. To perform the presented work, a compact model is developed considering interface traps, implemented in Verilog-A, and validated against experimental data of MoS2 based FETs. The compact model implemented in Verilog-A and extracted model parameters using IC-CAP are further used in the CAD tool Cadence® Virtuoso to perform circuit design and simulation analysis. The inverter circuit design and analysis in Cadence® Virtuoso shows that interface traps in both driver and load transistors can impact the inverter's static and dynamic behavior. The impact of interface traps in driver and load transistors on inverter performance are different. An increasing impact on inverter performance is visible with increasing interface traps. The inverter's static and dynamic behavior considered in the study are voltage transfer characteristics, gain, noise margin, delay, power, and power delay product.