Design space exploration of a particle filter using higher-0rder functions

Rinse Wester, Jan Kuper

    Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

    2 Citations (Scopus)
    8 Downloads (Pure)


    This paper presents a design space exploration methodology based on higher-order functions to facilitate the tradeoff between execution time and area usage on FPGAs. Higher-order function are transformed, resulting in parameterized nodes where the amount of parallelism and thereby performance, can be controlled. For composition and scheduling of operations, dataflow principles are used. To show the validity of the approach, a particle filter has been transformed and synthesized for FPGA. The resulting architecture is parameterizable and achieves good performance.
    Original languageUndefined
    Title of host publicationReconfigurable Computing: Architectures, Tools, and Applications
    Place of PublicationLondon
    Number of pages8
    ISBN (Print)978-3-319-05959-4
    Publication statusPublished - 2014
    Event10th International Symposium on Reconfigurable Computing, ARC 2014 - Vilamoura, Portugal
    Duration: 14 Apr 201416 Apr 2014

    Publication series

    NameLecture Notes in Computer Science
    PublisherSpringer Verlag
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349


    Conference10th International Symposium on Reconfigurable Computing, ARC 2014
    OtherApril 14-16, 2014


    • EWI-24700
    • Tradeoff
    • IR-90642
    • Higher-order functions
    • METIS-305870
    • Particle filter

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