Abstract
| Original language | Undefined |
|---|---|
| Title of host publication | Reconfigurable Computing: Architectures, Tools, and Applications |
| Place of Publication | London |
| Publisher | Springer |
| Pages | 219-226 |
| Number of pages | 8 |
| ISBN (Print) | 978-3-319-05959-4 |
| DOIs | |
| Publication status | Published - 2014 |
Publication series
| Name | Lecture Notes in Computer Science |
|---|---|
| Publisher | Springer Verlag |
| Number | 8405 |
| Volume | 8405 |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Keywords
- EWI-24700
- Tradeoff
- IR-90642
- Higher-order functions
- METIS-305870
- Particle filter
Cite this
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Design space exploration of a particle filter using higher-0rder functions. / Wester, Rinse; Kuper, Jan.
Reconfigurable Computing: Architectures, Tools, and Applications. London : Springer, 2014. p. 219-226 (Lecture Notes in Computer Science; Vol. 8405, No. 8405).Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review
TY - CHAP
T1 - Design space exploration of a particle filter using higher-0rder functions
AU - Wester, Rinse
AU - Kuper, Jan
N1 - 10.1007/978-3-319-05960-0_21
PY - 2014
Y1 - 2014
N2 - This paper presents a design space exploration methodology based on higher-order functions to facilitate the tradeoff between execution time and area usage on FPGAs. Higher-order function are transformed, resulting in parameterized nodes where the amount of parallelism and thereby performance, can be controlled. For composition and scheduling of operations, dataflow principles are used. To show the validity of the approach, a particle filter has been transformed and synthesized for FPGA. The resulting architecture is parameterizable and achieves good performance.
AB - This paper presents a design space exploration methodology based on higher-order functions to facilitate the tradeoff between execution time and area usage on FPGAs. Higher-order function are transformed, resulting in parameterized nodes where the amount of parallelism and thereby performance, can be controlled. For composition and scheduling of operations, dataflow principles are used. To show the validity of the approach, a particle filter has been transformed and synthesized for FPGA. The resulting architecture is parameterizable and achieves good performance.
KW - EWI-24700
KW - Tradeoff
KW - IR-90642
KW - Higher-order functions
KW - METIS-305870
KW - Particle filter
U2 - 10.1007/978-3-319-05960-0_21
DO - 10.1007/978-3-319-05960-0_21
M3 - Chapter
SN - 978-3-319-05959-4
T3 - Lecture Notes in Computer Science
SP - 219
EP - 226
BT - Reconfigurable Computing: Architectures, Tools, and Applications
PB - Springer
CY - London
ER -