Design space exploration of a particle filter using higher-0rder functions

Rinse Wester; Jan Kuper

doi:10.1007/978-3-319-05960-0_21

Design space exploration of a particle filter using higher-0rder functions

Rinse Wester
, Jan Kuper

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

2 Citations (Scopus)

9 Downloads (Pure)

Abstract

This paper presents a design space exploration methodology based on higher-order functions to facilitate the tradeoff between execution time and area usage on FPGAs. Higher-order function are transformed, resulting in parameterized nodes where the amount of parallelism and thereby performance, can be controlled. For composition and scheduling of operations, dataflow principles are used. To show the validity of the approach, a particle filter has been transformed and synthesized for FPGA. The resulting architecture is parameterizable and achieves good performance.

Original language	Undefined
Title of host publication	Reconfigurable Computing: Architectures, Tools, and Applications
Place of Publication	London
Publisher	Springer
Pages	219-226
Number of pages	8
ISBN (Print)	978-3-319-05959-4
DOIs	https://doi.org/10.1007/978-3-319-05960-0_21
Publication status	Published - 2014
Event	10th International Symposium on Reconfigurable Computing, ARC 2014 - Vilamoura, Portugal Duration: 14 Apr 2014 → 16 Apr 2014

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer Verlag
Number	8405
Volume	8405
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	10th International Symposium on Reconfigurable Computing, ARC 2014
Period	14/04/14 → 16/04/14
Other	April 14-16, 2014

Keywords

EWI-24700
Tradeoff
IR-90642
Higher-order functions
METIS-305870
Particle filter

Access to Document

10.1007/978-3-319-05960-0_21

http://eprints.eemcs.utwente.nl/secure2/24700/01/ARC_paper.pdf

Cite this

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title = "Design space exploration of a particle filter using higher-0rder functions",

abstract = "This paper presents a design space exploration methodology based on higher-order functions to facilitate the tradeoff between execution time and area usage on FPGAs. Higher-order function are transformed, resulting in parameterized nodes where the amount of parallelism and thereby performance, can be controlled. For composition and scheduling of operations, dataflow principles are used. To show the validity of the approach, a particle filter has been transformed and synthesized for FPGA. The resulting architecture is parameterizable and achieves good performance.",

keywords = "EWI-24700, Tradeoff, IR-90642, Higher-order functions, METIS-305870, Particle filter",

author = "Rinse Wester and Jan Kuper",

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Wester, R & Kuper, J 2014, Design space exploration of a particle filter using higher-0rder functions. in Reconfigurable Computing: Architectures, Tools, and Applications. Lecture Notes in Computer Science, no. 8405, vol. 8405, Springer, London, pp. 219-226, 10th International Symposium on Reconfigurable Computing, ARC 2014, 14/04/14. https://doi.org/10.1007/978-3-319-05960-0_21

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