Designing a dataflow processor using CλaSH

A. Niedermeier, Rinse Wester, Rinse Wester, K.C. Rovers, C.P.R. Baaij, Jan Kuper, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    1 Citation (Scopus)
    174 Downloads (Pure)

    Abstract

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final netlist showed correct behaviour. We conclude that Haskell and CλaSH are well-suited to define hardware on a very high level of abstraction which is close to the mathematical description of the desired architecture. By using CλaSH, the designer does not have to care about internal implementation details like when designing with VHDL. The complete processor was described in 300 lines of code, some snippets are shown as illustration.
    Original languageUndefined
    Title of host publication28th Norchip Conference, NORCHIP 2010
    PublisherIEEE Circuits & Systems Society
    Pages69
    Number of pages4
    ISBN (Print)978-1-4244-8971-8
    DOIs
    Publication statusPublished - 15 Nov 2010
    Event28th Norchip Conference, NORCHIP 2010 - Tampere, Finland
    Duration: 15 Nov 201016 Nov 2010

    Publication series

    Name
    PublisherIEEE Circuits & Systems Society

    Conference

    Conference28th Norchip Conference, NORCHIP 2010
    Period15/11/1016/11/10
    Other15-16 November 2010

    Keywords

    • IR-74963
    • EWI-18904
    • METIS-271151

    Cite this