Designing correct digital systems

Egbert Molenkamp

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Original languageUndefined
    Title of host publicationSynthese- und Verifikationsverfahren auf der basis von VHDL
    Place of PublicationDortmund
    Pages19-22
    Number of pages4
    Publication statusPublished - 12 Mar 1991

    Keywords

    • METIS-119235

    Cite this