Designing correct digital systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	Undefined
Title of host publication	Synthese- und Verifikationsverfahren auf der basis von VHDL
Place of Publication	Dortmund
Pages	19-22
Number of pages	4
Publication status	Published - 12 Mar 1991

Keywords

@inproceedings{6d02cd16a89d4c69a040ba92914cb3ad,

title = "Designing correct digital systems",

keywords = "METIS-119235",

author = "Egbert Molenkamp",

year = "1991",

month = mar,

day = "12",

language = "Undefined",

isbn = "0933-6192",

pages = "19--22",

booktitle = "Synthese- und Verifikationsverfahren auf der basis von VHDL",

}