Designing outside rail constraints

Anne J. Annema, Bram Nauta, Ronald van Langevelde, Hans Tuinhout

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

17 Citations (Scopus)
58 Downloads (Pure)

Abstract

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.
Original languageEnglish
Title of host publicationIEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004)
Place of PublicationSan Francisco, USA
PublisherIEEE
Pages134-135
Number of pages8
ISBN (Print)0780382676
DOIs
Publication statusPublished - Feb 2004
EventIEEE International Solid-State Circuits Conference, ISSCC 2004 - San Francisco, United States
Duration: 15 Feb 200419 Feb 2004

Publication series

Name
PublisherIEEE
Volume1

Conference

ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2004
Abbreviated titleISSCC 2004
CountryUnited States
CitySan Francisco
Period15/02/0419/02/04

Fingerprint

Rails
Electric potential
Transistors
Oxides

Keywords

  • METIS-218888
  • IR-47894
  • EWI-14474

Cite this

Annema, A. J., Nauta, B., van Langevelde, R., & Tuinhout, H. (2004). Designing outside rail constraints. In IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004) (pp. 134-135). San Francisco, USA: IEEE. https://doi.org/10.1109/ISSCC.2004.1332630
Annema, Anne J. ; Nauta, Bram ; van Langevelde, Ronald ; Tuinhout, Hans. / Designing outside rail constraints. IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004). San Francisco, USA : IEEE, 2004. pp. 134-135
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keywords = "METIS-218888, IR-47894, EWI-14474",
author = "Annema, {Anne J.} and Bram Nauta and {van Langevelde}, Ronald and Hans Tuinhout",
year = "2004",
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doi = "10.1109/ISSCC.2004.1332630",
language = "English",
isbn = "0780382676",
publisher = "IEEE",
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booktitle = "IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004)",
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Annema, AJ, Nauta, B, van Langevelde, R & Tuinhout, H 2004, Designing outside rail constraints. in IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004). IEEE, San Francisco, USA, pp. 134-135, IEEE International Solid-State Circuits Conference, ISSCC 2004, San Francisco, United States, 15/02/04. https://doi.org/10.1109/ISSCC.2004.1332630

Designing outside rail constraints. / Annema, Anne J.; Nauta, Bram; van Langevelde, Ronald; Tuinhout, Hans.

IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004). San Francisco, USA : IEEE, 2004. p. 134-135.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AU - van Langevelde, Ronald

AU - Tuinhout, Hans

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AB - CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.

KW - METIS-218888

KW - IR-47894

KW - EWI-14474

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DO - 10.1109/ISSCC.2004.1332630

M3 - Conference contribution

SN - 0780382676

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Annema AJ, Nauta B, van Langevelde R, Tuinhout H. Designing outside rail constraints. In IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004). San Francisco, USA: IEEE. 2004. p. 134-135 https://doi.org/10.1109/ISSCC.2004.1332630