Designing outside rail constraints

Anne J. Annema; Bram Nauta; Ronald van Langevelde; Hans Tuinhout

doi:10.1109/ISSCC.2004.1332630

Designing outside rail constraints

Anne J. Annema, Bram Nauta, Ronald van Langevelde, Hans Tuinhout

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

18 Citations (Scopus)

172 Downloads (Pure)

Abstract

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.

Original language	English
Title of host publication	IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004)
Place of Publication	San Francisco, USA
Publisher	IEEE
Pages	134-135
Number of pages	8
ISBN (Print)	0780382676
DOIs	https://doi.org/10.1109/ISSCC.2004.1332630
Publication status	Published - Feb 2004
Event	IEEE International Solid-State Circuits Conference, ISSCC 2004 - San Francisco, United States Duration: 15 Feb 2004 → 19 Feb 2004

Publication series

Name
Publisher	IEEE
Volume	1

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2004
Abbreviated title	ISSCC 2004
Country/Territory	United States
City	San Francisco
Period	15/02/04 → 19/02/04

Keywords

METIS-218888
IR-47894
EWI-14474

Access to Document

10.1109/ISSCC.2004.1332630

01332630Final published version, 485 KB

Cite this

@inproceedings{4787d7a16fa14060b835d2bb53a70592,

title = "Designing outside rail constraints",

abstract = "CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.",

keywords = "METIS-218888, IR-47894, EWI-14474",

author = "Annema, {Anne J.} and Bram Nauta and {van Langevelde}, Ronald and Hans Tuinhout",

year = "2004",

month = feb,

doi = "10.1109/ISSCC.2004.1332630",

language = "English",

isbn = "0780382676",

publisher = "IEEE",

pages = "134--135",

booktitle = "IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004)",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2004, ISSCC 2004 ; Conference date: 15-02-2004 Through 19-02-2004",

}

TY - GEN

T1 - Designing outside rail constraints

AU - Annema, Anne J.

AU - Nauta, Bram

AU - van Langevelde, Ronald

AU - Tuinhout, Hans

PY - 2004/2

Y1 - 2004/2

N2 - CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.

AB - CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.

KW - METIS-218888

KW - IR-47894

KW - EWI-14474

U2 - 10.1109/ISSCC.2004.1332630

DO - 10.1109/ISSCC.2004.1332630

M3 - Conference contribution

SN - 0780382676

SP - 134

EP - 135

BT - IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004)

PB - IEEE

CY - San Francisco, USA

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2004

Y2 - 15 February 2004 through 19 February 2004

ER -