@inproceedings{4787d7a16fa14060b835d2bb53a70592,
title = "Designing outside rail constraints",
abstract = "CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds matching tolerances requiring active cancellation techniques. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin and thick-oxide transistors.",
keywords = "METIS-218888, IR-47894, EWI-14474",
author = "Annema, {Anne J.} and Bram Nauta and {van Langevelde}, Ronald and Hans Tuinhout",
year = "2004",
month = feb,
doi = "10.1109/ISSCC.2004.1332630",
language = "English",
isbn = "0780382676",
publisher = "IEEE",
pages = "134--135",
booktitle = "IEEE International Solid-State Circuits Conference, 2004 (ISSCC 2004)",
address = "United States",
note = "IEEE International Solid-State Circuits Conference, ISSCC 2004, ISSCC 2004 ; Conference date: 15-02-2004 Through 19-02-2004",
}