Plasmas are key for enabling technologies in modern ultra-large scale integrated (ULSI) circuit manufacturing. Since the modern ULSI circuit consists of 107-108 transistors, the back-end-of-line (BEOL) metallization process with a multi-level interconnection of these transistors is a major technological challenge. These advanced multi-level interconnections can only be made by using high density plasma-enhanced deposition and etching techniques. However, a plasma is also a very harsh environment to integrated circuit (IC) products. A plasma could generate an unintended high electrical field which stresses and degrades the underlying thin gate oxide layer of the metal-oxide-silicon (MOS) transistors and non-volatile memories (NVM) as well as the insulator of MIM capacitors. MOS, NVM and MIM capacitors are major elements which form IC’s. Therefore the yield and reliability of these IC products are degraded by plasma charging damage. How to detect, control and reduce plasma charging damage becomes a formidable challenge in modern IC technology. In this thesis, the ways to detect and reduce plasma charging damage in the context of back-end-of-line (BEOL) processes have been studied.