Abstract
Instruction injections or soft errors during execution on the CPU can cause serious system vulnerabilities. During the standard program flow of the processor, the injection of unauthorized instruction or the occurrence of an error in the expected instruction are the main conditions for potentially serious such vulnerabilities. With the execution of these unauthorized instructions, adversaries could exploit SoC and execute their own malicious program or get higher-level privileges on the system. On the other hand, non-intentional errors can potentially corrupt programs causing unintended executions or the cause of program crashes. Modern trusted architectures propose solutions for unauthorized execution on SoC with additional software mechanisms or extra hardware logic on the same untrusted SoC. Nevertheless, these SoCs can still be vulnerable, as long as deployed security detection mechanisms are embedded within the same SoC's fabric. Furthermore, validation mechanisms on the SoC increase the complexity and power consumption of the SoC. This paper presents DEV-PIM, a new, high-performance, and low-cost execution validation mechanism in SoCs with external DRAM memory. The proposed approach uses processing-in-memory (PIM) method to detect instruction injections or corrupted instructions by utilising basic computing resources on a standard DRAM device. DEV-PIM transfers instructions scheduled for execution on the CPU to the DRAM and validates them by comparing content with the trusted program record on the DRAM using PIM operations. By optimising the DRAM scheduling process validation tasks are only executed when memory access is idle. The CPU retains uninterrupted memory access and can continue its normal program flow without penalty. We evaluate DEV-PIM in an end-To-end DRAM-compatible environment and run a set of software benchmarks. On average, the proposed architecture is able to detect 98.46% of instruction injections for different validation. We also measured on average only 0.346% CPU execution overhead with DEV-PIM enabled.
Original language | English |
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Title of host publication | Proceedings - 2023 IEEE European Test Symposium, ETS 2023 |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Number of pages | 6 |
ISBN (Electronic) | 979-8-3503-3634-4, 979-8-3503-3633-7 (USB) |
ISBN (Print) | 979-8-3503-3635-1 |
DOIs | |
Publication status | Published - 2023 |
Event | 28th IEEE European Test Symposium, ETS 2023 - Venice, Italy Duration: 22 May 2023 → 26 May 2023 Conference number: 28 |
Publication series
Name | Proceedings of the European Test Workshop |
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Volume | 2023-May |
ISSN (Print) | 1530-1877 |
ISSN (Electronic) | 1558-1780 |
Conference
Conference | 28th IEEE European Test Symposium, ETS 2023 |
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Abbreviated title | ETS 2023 |
Country/Territory | Italy |
City | Venice |
Period | 22/05/23 → 26/05/23 |
Keywords
- 2024 OA procedure
- Execution Validation
- Processing-in-Memory
- Trusted Execution
- DRAM