The functions in electronic devices such as mobile phones are increasing, while their dimensions are shrinking every year. To comply with this trend, the number of components on the integrated circuits (IC’s) is drastically increasing and their performance such as the switching speed are improving every year as was observed by Gordon Moore in 1965 . Moore suggested that the number of active components on an IC will double every 18 months . Cramming more components into integrated circuits necessitates the lateral and vertical shrinkage of the component dimensions. The International Technology Roadmap for Semiconductors (ITRS) foresees several challenges in complying with Moore’s law in future semiconductor devices , among which two reasons are worth noting. Firstly, the calculations of tunnel current through the dielectric layers by Hirose et al., based on multiplescattering theory show that the transconductance fluctuations will be problematic when the gate oxide thickness is scaled down to 0.8 nm . This sets the fundamental limit for thinning down the gate oxide (SiO2) in complementary metal-oxide-semiconductor (CMOS) devices to 0.7 nm, beyond which the spill-over of the silicon conduction-band wave-functions into the oxide generates interface states that will generate unacceptably large power consumption . Secondly, every bit of data processed in a CMOS logic gate consists of a thermodynamically irreversible process, which is given by the Landauer limit k T ln 2 B = 17.9 meV , which might set the noise limit beyond which the CMOS technology may not be possible unless another smart technology is developed .
|Award date||6 Oct 2010|
|Place of Publication||Oisterwijk|
|Publication status||Published - 6 Oct 2010|