A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1, 40-2, 40-n) are used may be changed in different samples. The current sources (40-1, 40-2, 40-n) may be replaced by one bit switched capacitor converters or by inverters connected to one end of a set of resistors, the other ends of which are connected to the virtual ground for an operational amplifier or alternatively to each other and arranged to directly generate the output voltage. According to one embodiment of the invention there is provided a sigma-delta analogue to digital converter comprising the circuit of the first aspect.; A method is also provided which can be done by controlling each source with a duty cycle of M/2n, where n is the required resolution of the converter and M is the input word, and controlling different sources with a time shift. This allows an equal contribution from all the elements in one sample period with reduced switching and low sensitivity for time jitter.
|Publication status||Submitted - 6 Dec 2002|