Digital-to-Frequency Converters with a DTC: Theoretical Analysis of the Output SFDR

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    Abstract

    In this paper, we propose and analyze a pulse-output digital-to-frequency converter (DFC) generating square waves, which uses a digital-to-time converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system, and explore possibilities and limits of this approach in terms of cleanness of the output spectrum. The behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worst-case spur, which leads to a simple design equation. This is useful to determine the DTC requirements [number of bits and integral non-linearity (INL)], given a certain spurious-free dynamic range (SFDR) target. We show that the maximum spur strength (in dBc) depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL, and other impairments) and increases with the ratio by 6 dB/octave.

    Original languageEnglish
    Article number8725932
    Pages (from-to)3761-3774
    Number of pages14
    JournalIEEE transactions on circuits and systems I: regular papers
    Volume66
    Issue number10
    Early online date29 May 2019
    DOIs
    Publication statusPublished - 1 Oct 2019

    Keywords

    • Delays
    • Clocks
    • frequency synthesizer
    • Phase locked loops
    • Frequency control
    • Frequency modulation
    • Mathematical model

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