Digital-to-time converters for spur correction in digital frequency synthesis

Claudia Palattella

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    30 Downloads (Pure)

    Abstract

    The demand for wireless communication, mobile computing and multifunctional portable electronics has driven System-on-Chip (SoC) solutions, where many functional blocks running at difference clock frequencies coexist on the same chip. This requires an on-chip clock source that must be able to generate a wide range of frequencies in a flexible way. The concept of Pulse-Output Digital-to-Frequency Converter (DFC) has been the starting point for the research developed in this thesis. A key limitation of this architecture is deterministic jitter, due to periodic phase errors produced by its digital core. The research described in this thesis focuses on reducing the deterministic jitter exploiting Digital-to-Time Converters (DTCs). The design of a new fully-differential DTC, suitable for GHz operating frequencies, is developed. To characterize the DTC in terms of resolution and linearity, we propose a method to measure its delay steps with unprecedented time resolution, as low as femto-seconds, with common lab equipment. The method exploits digital phase modulation to produce spurs related to the size of the DTC delay-steps. To correct the deterministic jitter of a Pulse-Output DFC, we propose in this thesis a spur correction with the aforementioned developed DTC. The system analysis shows that a 11-bit DTC with a few LSB INL is capable to push down the sub-harmonics spurs of the Pulse-Output DFC to -60 dBc. A mathematical model is derived that (1) predicts the strength of all the sub-harmonic spurs and (2) relates the maximum spur to the DTC Integral Non-Linearity (INL) in a simple, closed-form expression. This allows the designer to derive DTC INL requirements given a Spurious-Free Dynamic Range (SFDR) target. A fully-integrated prototype of a Pulse-Output DFC with DTC-based spur correction has been implemented in 1.2V 65nm CMOS technology. Measured worst case spurs are < -44dBc for an arbitrarily programmable frequency up to 500 MHz, with a power consumption of 51mW. Overall, it is shown that the spur-reduction technique based on DTC correction is promising for flexible digitally programmable frequency synthesis.
    Original languageEnglish
    QualificationDoctor of Philosophy
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Nauta, Bram , Supervisor
    • Klumperink, Eric A.M., Co-Supervisor
    Award date8 Jul 2020
    Place of PublicationEnschede
    Publisher
    Print ISBNs978-90-365-5015-4
    DOIs
    Publication statusPublished - 8 Jul 2020

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