The increasing amount of data produced in satellites poses a problem for the limited data rate of its
downlink. This discrepancy is solved by introducing more and more processing power on-board to compress
data to a satisfiable rate. Currently, this processing power is often provided by custom-off-the-shelf hardware.
These architectures introduce problems when they are scaled up. To deal with the ever increasing data rate
of the newest sensors and still be within the same power and thermal constraints, new architectures are being
In this paper we will describe one of these new architectures, the Montium tile processor, and we show
how a well-known algorithm, the CCSDS 9/7 integer discrete wavelet transform (DWT), can be mapped to
this architecture. Furthermore, some improvements are discussed that can make the Montium and reconfigurable
architectures in general, an even better platform to support algorithms like the DWT.
|Publisher||ESA conference bureau|
|Conference||On-Board Payload Data Compression Workshop 2008, Noordwijk|
|Period||27/06/08 → …|