Distortion mitigation in cognitive radio receivers

The exponential increase of wireless communication increasingly leads to spectrum congestion. Attempts are being made to increase RF spectrum utilization efficiency by introducing Cognitive Radio (CR) concept. A CR tries to intelligently solve the congestion problem via Dynamic Spectrum Access (DSA), i.e. determine which frequencies are temporarily and locally free, and exploit this free spectrum. Especially in the TV broadcasting bands below 1 GHz, such CR possibilities are being explored. Ideally, a CR receiver should be able to operate directly adjacent to the primary service users, e.g. Digital TV channels, which use high power levels and often leave the adjacent channels unused. Under such conditions no or very low up-front filtering of the interferer is possible. Consequently, a CR receiver must tolerate the existence of strong interferers, i.e. have a very high linearity front-end. This thesis examines CR receiver linearity requirements and explores techniques that mitigate distortion. The thesis starts by analyzing the linearity requirements for DSA. As the level and the spectral location of the interferers can change instantaneously per location, it is relevant to monitor the spectrum and find suitable opportunities for communication. The analysis is applied to a channelized spectrum in which a number of interferers exist, and a CR tries to exploit any free channel. It is derived how the CR linearity requirement depends not just on the power levels of the interferers but also on their spectral locations around the desired CR frequency/channel. It is shown that the linearity requirement can be relaxed by tens of dBs levels of 3rd order InterModulation product (IM3). The analysis also exploits the prediction of the distortions in different channels for DSA. This prediction algorithm is denoted here as DPrA (i.e. Distortion Prediction Algorithm). It processes the spectrum sensing information about the power level and the spectral locations of the interferers to derive the linearity requirements for each potential CR channel. Based on this information, a CR can choose the most suitable channel compatible with its linearity capability. A receiver with better linearity can work under worse interference conditions, and hence maximizing linearity of a CR receiver is important. To increase the linearity of a CR receiver, CMOS receiver frontends with high linearity are explored. Receivers that exploit linear V-I conversion at RF, followed by passive down-mixing and an OpAmp-based Transimpedance Amplifier at baseband, show high linearity potential. However, it is shown that due to nonlinearity and finite gain in the OpAmp, the virtual ground II is imperfect, resulting in distortion currents. The concept of a negative conductance is proposed to cancel such distortion currents. Through a simple intuitive analysis, the basic operation of the technique is explained. By mathematical analysis the optimum negative conductance value is derived and related to feedback theory. It is shown that a finite value of the negative conductance is needed to make the feedback loopgain theoretically approach infinity, which is practically not easily possible by increasing the gain of the OpAmp block. The technique is applied to linearize an RF receiver and a prototype is implemented in 65nm technology. Measurement results show an increase of the in-band IIP3 from 9dBm to >20dBm, and IIP2 from 51 to 61dBm, at the cost of an increase of the noise figure from 6 to 7.5dB and <10% power penalty. The chip achieves a Spurious-Free Dynamic Range of 85dB in 1MHz.