Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time

Daniel Schinkel; E. Mensink; Eric A.M. Klumperink; Adrianus Johannes Maria van Tuijl; Bram Nauta

doi:10.1109/ISSCC.2007.373420

Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time

Daniel Schinkel, E. Mensink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

662 Citations (Scopus)

1059 Downloads (Pure)

Abstract

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference (ISSCC)
Place of Publication	Piscataway
Publisher	IEEE
Pages	314-315
Number of pages	3
ISBN (Print)	1-4244-0852-0
DOIs	https://doi.org/10.1109/ISSCC.2007.373420
Publication status	Published - 13 Feb 2007
Event	IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco Marriott, San Francisco, United States Duration: 3 Feb 2007 → 7 Feb 2007

Conference

Conference	IEEE International Solid-State Circuits Conference, ISSCC 2007
Abbreviated title	ISSCC
Country/Territory	United States
City	San Francisco
Period	3/02/07 → 7/02/07

Keywords

EWI-9993
IR-64054
METIS-245719

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10.1109/ISSCC.2007.373420

04bcc4b425b4430671b88e116a9b8ea1Final published version, 1.06 MB

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title = "Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time",

abstract = "A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time",

keywords = "EWI-9993, IR-64054, METIS-245719",

author = "Daniel Schinkel and E. Mensink and Klumperink, {Eric A.M.} and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "2007",

month = feb,

day = "13",

doi = "10.1109/ISSCC.2007.373420",

language = "English",

isbn = "1-4244-0852-0",

pages = "314--315",

booktitle = "2007 IEEE International Solid-State Circuits Conference (ISSCC)",

publisher = "IEEE",

address = "United States",

note = "IEEE International Solid-State Circuits Conference, ISSCC 2007, ISSCC ; Conference date: 03-02-2007 Through 07-02-2007",

}

Schinkel, D, Mensink, E, Klumperink, EAM, van Tuijl, AJM & Nauta, B 2007, Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. in 2007 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, Piscataway, pp. 314-315, IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, California, United States, 3/02/07. https://doi.org/10.1109/ISSCC.2007.373420

TY - GEN

T1 - Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time

AU - Schinkel, Daniel

AU - Mensink, E.

AU - Klumperink, Eric A.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

PY - 2007/2/13

Y1 - 2007/2/13

N2 - A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

AB - A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

KW - EWI-9993

KW - IR-64054

KW - METIS-245719

U2 - 10.1109/ISSCC.2007.373420

DO - 10.1109/ISSCC.2007.373420

M3 - Conference contribution

SN - 1-4244-0852-0

SP - 314

EP - 315

BT - 2007 IEEE International Solid-State Circuits Conference (ISSCC)

PB - IEEE

CY - Piscataway

T2 - IEEE International Solid-State Circuits Conference, ISSCC 2007

Y2 - 3 February 2007 through 7 February 2007

ER -

Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time

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Keywords

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