Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time

Daniel Schinkel, E. Mensink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

349 Citations (Scopus)
57 Downloads (Pure)

Abstract

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time
Original languageEnglish
Title of host publication2007 IEEE International Solid-State Circuits Conference (ISSCC)
Place of PublicationPiscataway
PublisherIEEE
Pages314-315
Number of pages3
ISBN (Print)1-4244-0852-0
DOIs
Publication statusPublished - 13 Feb 2007
EventIEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco Marriott, San Francisco, United States
Duration: 3 Feb 20077 Feb 2007

Conference

ConferenceIEEE International Solid-State Circuits Conference, ISSCC 2007
Abbreviated titleISSCC
CountryUnited States
CitySan Francisco
Period3/02/077/02/07

Fingerprint

Electric potential
Networks (circuits)

Keywords

  • EWI-9993
  • IR-64054
  • METIS-245719

Cite this

Schinkel, D., Mensink, E., Klumperink, E. A. M., van Tuijl, A. J. M., & Nauta, B. (2007). Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. In 2007 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 314-315). Piscataway: IEEE. https://doi.org/10.1109/ISSCC.2007.373420
Schinkel, Daniel ; Mensink, E. ; Klumperink, Eric A.M. ; van Tuijl, Adrianus Johannes Maria ; Nauta, Bram. / Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. 2007 IEEE International Solid-State Circuits Conference (ISSCC). Piscataway : IEEE, 2007. pp. 314-315
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abstract = "A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time",
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Schinkel, D, Mensink, E, Klumperink, EAM, van Tuijl, AJM & Nauta, B 2007, Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. in 2007 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, Piscataway, pp. 314-315, IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, United States, 3/02/07. https://doi.org/10.1109/ISSCC.2007.373420

Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. / Schinkel, Daniel; Mensink, E.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram.

2007 IEEE International Solid-State Circuits Conference (ISSCC). Piscataway : IEEE, 2007. p. 314-315.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

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Schinkel D, Mensink E, Klumperink EAM, van Tuijl AJM, Nauta B. Double-Tail latch-type voltage sense amplifier with 18ps setup+hold time. In 2007 IEEE International Solid-State Circuits Conference (ISSCC). Piscataway: IEEE. 2007. p. 314-315 https://doi.org/10.1109/ISSCC.2007.373420