Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Scott W. Fong; Christopher M. Neumann; Eilam Yalon; Miguel Munoz Rojo; Eric Pop; H. S.Philip Wong

doi:10.1109/TED.2017.2756071

Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Scott W. Fong^*, Christopher M. Neumann, Eilam Yalon, Miguel Munoz Rojo, Eric Pop, H. S.Philip Wong (Corresponding Author)

^*Corresponding author for this work

Research output: Contribution to journal › Article › Academic › peer-review

29 Citations (Scopus)

Abstract

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO₂/Al₂O₃ insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm². Implementing the DLS enables a 60% reduction in reset energy compared with SiO₂-isolated devices.

Original language	English
Article number	8076849
Pages (from-to)	4496-4502
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	64
Issue number	11
DOIs	https://doi.org/10.1109/TED.2017.2756071
Publication status	Published - Nov 2017
Externally published	Yes

Keywords

Phase-change memory (PCM)
reset energy
thermal conductivity
thermal design

Access to Document

10.1109/TED.2017.2756071

Cite this

@article{b34587b6e2f44bda9fa47ee5ad92670e,

title = "Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory",

abstract = "High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.",

keywords = "Phase-change memory (PCM), reset energy, thermal conductivity, thermal design",

author = "Fong, {Scott W.} and Neumann, {Christopher M.} and Eilam Yalon and Rojo, {Miguel Munoz} and Eric Pop and Wong, {H. S.Philip}",

year = "2017",

month = nov,

doi = "10.1109/TED.2017.2756071",

language = "English",

volume = "64",

pages = "4496--4502",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "IEEE",

number = "11",

}

TY - JOUR

T1 - Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

AU - Fong, Scott W.

AU - Neumann, Christopher M.

AU - Yalon, Eilam

AU - Rojo, Miguel Munoz

AU - Pop, Eric

AU - Wong, H. S.Philip

PY - 2017/11

Y1 - 2017/11

N2 - High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.

AB - High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 to 20 nm and lengths of 2~ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.

KW - Phase-change memory (PCM)

KW - reset energy

KW - thermal conductivity

KW - thermal design

UR - http://www.scopus.com/inward/record.url?scp=85036641969&partnerID=8YFLogxK

U2 - 10.1109/TED.2017.2756071

DO - 10.1109/TED.2017.2756071

M3 - Article

AN - SCOPUS:85036641969

SN - 0018-9383

VL - 64

SP - 4496

EP - 4502

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 11

M1 - 8076849

ER -

Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this