Dynamic Voltage and Frequency Scaling and Adaptive Body Biasing for Active and Leakage Power Reduction in MPSoC: a Literature Overview

A. Milutinovic, Anca Molnos, Kees Goossens, Gerardus Johannes Maria Smit

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    Abstract

    Power is an important design constraint for all nomadic and tethered devices as mobile phones or media-boxes today. This is mainly because it limits their operational time or because of the required operational thermal conditions. In order to keep the pace with increasing number of use-cases while increasing the lifetime, power reduction is enforced to all parts of a device, thus also for the embedded chipset. For this and other reasons like cost and size, the whole chipset has been integrated into a multiprocessor system-on-chip (MPSOC). As a complex and often heterogeneous system that executes different mixtures of applications with the variable workload, not all of its parts are utilized all the time. This introduces spare time in the system, denoted as slack that is possible to exploit for lower power and energy consumption by power management (PM). The most common techniques are adaptive body biasing and dynamic voltage and frequency scaling of a part of a system or the system as a whole. The scope of our research is power management including these techniques on an MPSoC executing streaming applications, such as audio/video codecs, telecom services (protocols), or any other firm and soft real time applications. A lot of previous research has been done on this topic, mostly focusing on the isolated parts of the system. However, focus has recently been moved to the system-wise approach. This paper is an overview of the commercial and solutions from academia, published until now. Special attention is given to the state-of-the-art infrastructure for PM and its dynamic possibilities to react and save power. We favourite the conservative approaches that do not disturb regular execution and do not introduce any additional delay or deadline misses comparing to the execution without power management. An overview of advanced PM is presented. Additionally, we elaborate the trade-off between race-to-idle and performance-on demand approaches reflecting the difference in static and dynamic power consumption.
    Original languageUndefined
    Title of host publicationProceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2009
    Place of PublicationUtrecht
    PublisherSTW
    Pages488-495
    Number of pages8
    ISBN (Print)978-90-73461-62-8
    Publication statusPublished - 27 Nov 2009
    Event20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009 - Veldhoven, Netherlands
    Duration: 26 Nov 200927 Nov 2009
    Conference number: 20

    Publication series

    Name
    PublisherTechnology Foundation / SAFE &ProRISC

    Conference

    Conference20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009
    CountryNetherlands
    CityVeldhoven
    Period26/11/0927/11/09

    Keywords

    • IR-69387
    • METIS-264236
    • overview
    • System on Chip
    • tiled architecture
    • CAES-EEA: Efficient Embedded Architectures
    • EWI-16996
    • slack exploitation
    • dynamic power reduction

    Cite this

    Milutinovic, A., Molnos, A., Goossens, K., & Smit, G. J. M. (2009). Dynamic Voltage and Frequency Scaling and Adaptive Body Biasing for Active and Leakage Power Reduction in MPSoC: a Literature Overview. In Proceedings of the Program for research on Ingrated systems and Circuits (ProRISC) 2009 (pp. 488-495). Utrecht: STW.