ECR plasma deposited SiO2 and Si3N4 layers: a room temperature technology

Gratiela Ileana Isai

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    40 Downloads (Pure)


    PMOSFETs with gate dielectrics deposited by multipolar ECR plasma source at 5000C and near room temperatures have been fabricated with a simple and fast manufacturing process. The transistors exhibited low threshold voltage (-1,25 V, -2.5 V), reasonably high mobilities (101 cm2/Vs), low off-currents 10-12 A) and subthreshold slopes (~ 0.3 V/dec.). Decreasing the deposition temperature of the gate dielectric did not considerably degrade the transistor parameters. The reference MOSFETs with thermally grown (10500C) SiO2 had superior characteristics. However, the transistors with low temperature dielectrics were reasonably good, considering the temperature used. Thin film n-channel transistors with large grain silicon and low temperature ECR gate dielectric exhibited high mobilities (300-400 cm2/Vs) and low threshold voltage of -1 V. The off current of these devices was rather high.
    Original languageEnglish
    Awarding Institution
    • University of Twente
    • Wallinga, H., Supervisor
    • Woerlee, P.H., Supervisor
    • Holleman, J., Co-Supervisor
    Thesis sponsors
    Award date27 Jun 2003
    Place of PublicationEnschede
    Print ISBNs90-365-1934-9
    Publication statusPublished - 27 Jun 2003


    • METIS-214268
    • IR-41455
    • EWI-15705


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