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Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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    Abstract

    A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buffers in order to control jitter. This requires the derivation of buffer capacities that both satisfy the temporal constraints as well as constraints on the buffer capacity. Existing exact solutions suffer from the computational complexity associated with the required conversion from a multi-rate dataflow graph to a single-rate dataflow graph. In this paper we present an algorithm, with linear computational complexity, that does not require this conversion and that determines close to minimal buffer capacities. The algorithm is applied to an MP3 play-back application that is mapped on our network based multi-processor system.
    Original languageEnglish
    Title of host publicationCODES+ISSS '06
    Subtitle of host publicationProceedings of the 4th International Conference on Hardware/Software Codesign an System Synthesis
    Place of PublicationNew York, NY
    PublisherAssociation for Computing Machinery
    Pages10-15
    Number of pages6
    ISBN (Print)1-59593-370-0
    DOIs
    Publication statusPublished - Oct 2006
    Event4th International Conference on Hardware/Software Codesign an System Synthesis, CODES+ISSS 2006 - Seoul, Korea, Republic of
    Duration: 22 Oct 2006 → 25 Oct 2006
    Conference number: 4

    Conference

    Conference4th International Conference on Hardware/Software Codesign an System Synthesis, CODES+ISSS 2006
    Abbreviated titleCODES+ISSS
    Country/TerritoryKorea, Republic of
    CitySeoul
    Period22/10/06 → 25/10/06

    Keywords

    • 2020 OA procedure
    • CAES-EEA: Efficient Embedded Architectures

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