Efficient implementation of 8-bit vedic multipliers for image processing application

Aravind E Vijayan; Arlene John; Deepak Sen

doi:10.1109/IC3I.2014.7019675

Efficient implementation of 8-bit vedic multipliers for image processing application

Aravind E Vijayan
, Arlene John
, Deepak Sen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Vedic mathematics is an Ancient Indian system of mathematics which was rediscovered in the early twentieth century. In this paper, A high speed and area efficient 8-bit vedic multiplier architecture is proposed so as to implement faster real time hardware image processing. The system was implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator. A comparative analysis have been performed and the proposed architecture was found to be efficient both in terms of area and total propagation delay.

Original language	English
Title of host publication	2014 International Conference on Contemporary Computing and Informatics (IC3I)
Pages	544-552
ISBN (Electronic)	978-1-4799-6629-5
DOIs	https://doi.org/10.1109/IC3I.2014.7019675
Publication status	Published - 26 Jan 2015
Externally published	Yes
Event	International Conference on Contemporary Computing and Informatics, IC3I 2014 - Mysore, India Duration: 27 Nov 2014 → 29 Nov 2014

Conference

Conference	International Conference on Contemporary Computing and Informatics, IC3I 2014
Abbreviated title	IC3I 2014
Country/Territory	India
City	Mysore
Period	27/11/14 → 29/11/14

Keywords

n/a OA procedure

Access to Document

10.1109/IC3I.2014.7019675

Cite this

@inproceedings{ac85467ca1884649b16583e455f3d8b4,

title = "Efficient implementation of 8-bit vedic multipliers for image processing application",

abstract = "Vedic mathematics is an Ancient Indian system of mathematics which was rediscovered in the early twentieth century. In this paper, A high speed and area efficient 8-bit vedic multiplier architecture is proposed so as to implement faster real time hardware image processing. The system was implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator. A comparative analysis have been performed and the proposed architecture was found to be efficient both in terms of area and total propagation delay.",

keywords = "n/a OA procedure",

author = "\{E Vijayan\}, Aravind and Arlene John and Deepak Sen",

year = "2015",

month = jan,

day = "26",

doi = "10.1109/IC3I.2014.7019675",

language = "English",

pages = "544--552",

booktitle = "2014 International Conference on Contemporary Computing and Informatics (IC3I)",

note = "International Conference on Contemporary Computing and Informatics, IC3I 2014, IC3I 2014 ; Conference date: 27-11-2014 Through 29-11-2014",

}

TY - GEN

T1 - Efficient implementation of 8-bit vedic multipliers for image processing application

AU - E Vijayan, Aravind

AU - John, Arlene

AU - Sen, Deepak

PY - 2015/1/26

Y1 - 2015/1/26

N2 - Vedic mathematics is an Ancient Indian system of mathematics which was rediscovered in the early twentieth century. In this paper, A high speed and area efficient 8-bit vedic multiplier architecture is proposed so as to implement faster real time hardware image processing. The system was implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator. A comparative analysis have been performed and the proposed architecture was found to be efficient both in terms of area and total propagation delay.

AB - Vedic mathematics is an Ancient Indian system of mathematics which was rediscovered in the early twentieth century. In this paper, A high speed and area efficient 8-bit vedic multiplier architecture is proposed so as to implement faster real time hardware image processing. The system was implemented on Xilinx Virtex 4 based FPGA board and the performance was evaluated using Xilinx ISim simulator. A comparative analysis have been performed and the proposed architecture was found to be efficient both in terms of area and total propagation delay.

KW - n/a OA procedure

U2 - 10.1109/IC3I.2014.7019675

DO - 10.1109/IC3I.2014.7019675

M3 - Conference contribution

SP - 544

EP - 552

BT - 2014 International Conference on Contemporary Computing and Informatics (IC3I)

T2 - International Conference on Contemporary Computing and Informatics, IC3I 2014

Y2 - 27 November 2014 through 29 November 2014

ER -

Efficient implementation of 8-bit vedic multipliers for image processing application

Abstract

Conference

Keywords

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Cite this