Abstract
The IEEE 1687 standard introduced a large design space of compliant networks for accessing embedded instruments. Such networks could grow in their structural complexity and inter-component temporal dependencies. Scan pattern retargeting is defined as the procedure of translating an instrument-level pattern to several network-level ones. Pattern retargeting could become computationally intensive with the increase of structural and temporal dependencies. Structured pattern retargeting was previously introduced as a formal and light-weight pattern retargeting methodology for arbitrary IEEE 1687 networks. In this work, we present a dedicated structured retargeting method for hierarchical IEEE 1687 networks. The proposed method significantly reduces the retargeting time for pure hierarchical networks compared to the general one, while resulting in the same network access time. The retargeting time is of a special importance in the case of on-chip retargeting, which is used for on-line monitoring using IEEE 1687 networks.
Original language | English |
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Title of host publication | IEEE VLSI Test Symposium (VTS) |
Subtitle of host publication | VTS 2019: proceedings: April 23rd - 25th 2019, Monterey, California (USA) |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 1-6 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-7281-1170-4 |
DOIs | |
Publication status | Published - 23 Apr 2019 |
Event | 37th IEEE VLSI Test Symposium, VLSI 2019: Test Reliability and Security Challenges in VLSI Systems - Monterey, United States Duration: 23 Apr 2019 → 25 Apr 2019 |
Conference
Conference | 37th IEEE VLSI Test Symposium, VLSI 2019 |
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Abbreviated title | VLSI 2019 |
Country/Territory | United States |
City | Monterey |
Period | 23/04/19 → 25/04/19 |
Keywords
- Embedded Instruments
- IEEE 1687 Standard
- IJTAG
- Structured retargeting