Abstract
| Original language | Undefined |
|---|---|
| Title of host publication | 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) |
| Place of Publication | USA |
| Publisher | IEEE Computer Society |
| Pages | 97-102 |
| Number of pages | 6 |
| ISBN (Print) | 978-1-5090-3623-3 |
| DOIs | |
| Publication status | Published - 19 Sep 2016 |
| Event | 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016 - University of Connecticut, Storrs, United States Duration: 19 Sep 2016 → 20 Sep 2016 |
Publication series
| Name | |
|---|---|
| Publisher | IEEE Computer Society |
Conference
| Conference | 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016 |
|---|---|
| Abbreviated title | DFT |
| Country | United States |
| City | Storrs |
| Period | 19/09/16 → 20/09/16 |
Keywords
- EWI-27352
- METIS-318573
- IR-101897
Cite this
}
Efficient Utilization of Hierarchical iJTAG Networks for Interrupts Management. / Ibrahim, Ahmed Mohammed Youssef; Kerkhoff, Hans G.
2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). USA : IEEE Computer Society, 2016. p. 97-102.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Efficient Utilization of Hierarchical iJTAG Networks for Interrupts Management
AU - Ibrahim, Ahmed Mohammed Youssef
AU - Kerkhoff, Hans G.
N1 - eemcs-eprint-27352
PY - 2016/9/19
Y1 - 2016/9/19
N2 - Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for different reasons. For example, fault/event occurrences or measurement read-out requests; however iJTAG networks are inherently master/slave networks, where the instruments are the network slaves. In this work, a scalable interrupts-management methodology is presented for allowing instruments-initiated communication using hierarchical iJTAG networks. The presented method allows for an efficient access of the network according to the required use-case by allowing the network to be configured into a corresponding optimized mode. In addition, a novel on-chip localization methodology is presented, which significantly reduces the localization time of interrupting instruments as compared to previous works.
AB - Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for different reasons. For example, fault/event occurrences or measurement read-out requests; however iJTAG networks are inherently master/slave networks, where the instruments are the network slaves. In this work, a scalable interrupts-management methodology is presented for allowing instruments-initiated communication using hierarchical iJTAG networks. The presented method allows for an efficient access of the network according to the required use-case by allowing the network to be configured into a corresponding optimized mode. In addition, a novel on-chip localization methodology is presented, which significantly reduces the localization time of interrupting instruments as compared to previous works.
KW - EWI-27352
KW - METIS-318573
KW - IR-101897
U2 - 10.1109/DFT.2016.7684077
DO - 10.1109/DFT.2016.7684077
M3 - Conference contribution
SN - 978-1-5090-3623-3
SP - 97
EP - 102
BT - 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
PB - IEEE Computer Society
CY - USA
ER -