Abstract
The stress in deposited silicon dioxide and silicon nitride layers that are used in the fabrication of self-aligned bipolar transistor structures, is evaluated. The intrinsic and thermal stress of the layers is measured and these values are used in a finite element process simulator to calculate the pressure in the silicon around the emitter window during processing. Bipolar transistors are fabricated with different combinations of silicon oxide and silicon nitride and the yield of large transistor arrays is compared with the calculated pressure for the different combinations. The presence of a tensile pressure near the emitter coincides with a low measured device yield.
| Original language | English |
|---|---|
| Pages (from-to) | 339-341 |
| Number of pages | 3 |
| Journal | Journal of Materials Science: Materials in Electronics |
| Volume | 12 |
| Issue number | 4-6 |
| DOIs | |
| Publication status | Published - 1 Apr 2001 |
| Externally published | Yes |