Electrical detection and simulation of stress in silicon nitride spacer technology

H. W. Van Zeijl*, S. Mijalcovic, L. K. Nanver

*Corresponding author for this work

Research output: Contribution to journalArticleAcademicpeer-review

3 Citations (Scopus)

Abstract

The stress in deposited silicon dioxide and silicon nitride layers that are used in the fabrication of self-aligned bipolar transistor structures, is evaluated. The intrinsic and thermal stress of the layers is measured and these values are used in a finite element process simulator to calculate the pressure in the silicon around the emitter window during processing. Bipolar transistors are fabricated with different combinations of silicon oxide and silicon nitride and the yield of large transistor arrays is compared with the calculated pressure for the different combinations. The presence of a tensile pressure near the emitter coincides with a low measured device yield.

Original languageEnglish
Pages (from-to)339-341
Number of pages3
JournalJournal of Materials Science: Materials in Electronics
Volume12
Issue number4-6
DOIs
Publication statusPublished - 1 Apr 2001
Externally publishedYes

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