Electronic devices fabricated at CMOS backend-compatible temperatures

I. Brunets

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    150 Downloads (Pure)

    Abstract

    The number of transistors in integrated circuits is exponentially increasing over time, as predicted by Gordon Moore in the 1960s (e.g. 781 million transistors in the current Intel Xeon processor). This leads to higher computing power at a reduced cost per function. However, the future scaling perspective encounters several limiting factors, such as: an increased interconnect resistance-capacitance (RC) delay, enormous power densities – the so-called “power wall��?, and exploding costs due to the high process complexity. Therefore, further functionality growth within conventional planar ICs would not be possible without compromising on performance or cost, requiring drastic changes in the production process. Three-dimensional (3-D) integration of ICs, as already foreseen in the same ‘60s but thus far kept in the periphery of semiconductor technology, is nowadays gaining attention as an alternative to further lateral downscaling. It is highly attractive for application in mobile computing devices, where various functionalities have to be added to a single die to keep the system’s dimensions small.
    Original languageUndefined
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Schmitz, Jurriaan, Supervisor
    • Holleman, J., Advisor
    Thesis sponsors
    Award date17 Dec 2009
    Place of PublicationEnschede
    Publisher
    Print ISBNs978-90-365-2935-8
    DOIs
    Publication statusPublished - 17 Dec 2009

    Keywords

    • SC-ICF: Integrated Circuit Fabrication
    • IR-68886
    • EWI-17304
    • METIS-264497

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