Electrostatic Doping in Semiconductor Devices

Gaurav Gupta, Bijoy Rajasekharan, Raymond J.E. Hueting

    Research output: Contribution to journalArticleAcademicpeer-review

    16 Citations (Scopus)
    1 Downloads (Pure)

    Abstract

    To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED. The effect of interface traps on the induced charge is also addressed. In addition, we discuss the performance benefits of ED devices and the major roadblocks of these approaches for potential future CMOS technology.
    Original languageEnglish
    Pages (from-to)3044-3055
    Number of pages12
    JournalIEEE transactions on electron devices
    Volume64
    Issue number8
    DOIs
    Publication statusPublished - 23 Jun 2017

    Fingerprint

    Semiconductor devices
    Electrostatics
    Doping (additives)
    Energy gap
    Metals
    Electric fields
    Semiconductor materials
    Electrons

    Keywords

    • Doping
    • Logic gates
    • Metals
    • Schottky barriers
    • Silicon
    • Electrostatics
    • Charge carrier processes

    Cite this

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    title = "Electrostatic Doping in Semiconductor Devices",
    abstract = "To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED. The effect of interface traps on the induced charge is also addressed. In addition, we discuss the performance benefits of ED devices and the major roadblocks of these approaches for potential future CMOS technology.",
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    Electrostatic Doping in Semiconductor Devices. / Gupta, Gaurav ; Rajasekharan, Bijoy; Hueting, Raymond J.E.

    In: IEEE transactions on electron devices, Vol. 64, No. 8, 23.06.2017, p. 3044-3055.

    Research output: Contribution to journalArticleAcademicpeer-review

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    T1 - Electrostatic Doping in Semiconductor Devices

    AU - Gupta, Gaurav

    AU - Rajasekharan, Bijoy

    AU - Hueting, Raymond J.E.

    PY - 2017/6/23

    Y1 - 2017/6/23

    N2 - To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED. The effect of interface traps on the induced charge is also addressed. In addition, we discuss the performance benefits of ED devices and the major roadblocks of these approaches for potential future CMOS technology.

    AB - To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED. The effect of interface traps on the induced charge is also addressed. In addition, we discuss the performance benefits of ED devices and the major roadblocks of these approaches for potential future CMOS technology.

    KW - Doping

    KW - Logic gates

    KW - Metals

    KW - Schottky barriers

    KW - Silicon

    KW - Electrostatics

    KW - Charge carrier processes

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    JF - IEEE transactions on electron devices

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