Energy Model of Networks-on-Chip and a Bus

P.T. Wolkotte, Gerardus Johannes Maria Smit, N.K. Kavaldjiev, Jens E. Becker, Jurgen Becker

Research output: Book/ReportReportProfessional

41 Citations (Scopus)
35 Downloads (Pure)

Abstract

A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon- Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.
Original languageUndefined
Place of PublicationEnschede
PublisherCentre for Telematics and Information Technology (CTIT)
Number of pages5
Publication statusPublished - Jun 2005

Publication series

NameCTIT Technical Report Series
No.05-24
ISSN (Print)1381-3625

Keywords

  • EWI-737
  • CAES-EEA: Efficient Embedded Architectures
  • EC Grant Agreement nr.: FP6/001908
  • IR-54529
  • METIS-228785

Cite this

Wolkotte, P. T., Smit, G. J. M., Kavaldjiev, N. K., Becker, J. E., & Becker, J. (2005). Energy Model of Networks-on-Chip and a Bus. (CTIT Technical Report Series; No. 05-24). Enschede: Centre for Telematics and Information Technology (CTIT).
Wolkotte, P.T. ; Smit, Gerardus Johannes Maria ; Kavaldjiev, N.K. ; Becker, Jens E. ; Becker, Jurgen. / Energy Model of Networks-on-Chip and a Bus. Enschede : Centre for Telematics and Information Technology (CTIT), 2005. 5 p. (CTIT Technical Report Series; 05-24).
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Wolkotte, PT, Smit, GJM, Kavaldjiev, NK, Becker, JE & Becker, J 2005, Energy Model of Networks-on-Chip and a Bus. CTIT Technical Report Series, no. 05-24, Centre for Telematics and Information Technology (CTIT), Enschede.

Energy Model of Networks-on-Chip and a Bus. / Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jurgen.

Enschede : Centre for Telematics and Information Technology (CTIT), 2005. 5 p. (CTIT Technical Report Series; No. 05-24).

Research output: Book/ReportReportProfessional

TY - BOOK

T1 - Energy Model of Networks-on-Chip and a Bus

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AB - A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon- Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

KW - EWI-737

KW - CAES-EEA: Efficient Embedded Architectures

KW - EC Grant Agreement nr.: FP6/001908

KW - IR-54529

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Wolkotte PT, Smit GJM, Kavaldjiev NK, Becker JE, Becker J. Energy Model of Networks-on-Chip and a Bus. Enschede: Centre for Telematics and Information Technology (CTIT), 2005. 5 p. (CTIT Technical Report Series; 05-24).