Energy Model of Networks-on-Chip and a Bus

P.T. Wolkotte, Gerardus Johannes Maria Smit, N.K. Kavaldjiev, Jens E. Becker, Jurgen Becker

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    Abstract

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon- Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.
    Original languageUndefined
    Place of PublicationEnschede
    PublisherCentre for Telematics and Information Technology (CTIT)
    Number of pages5
    Publication statusPublished - Jun 2005

    Publication series

    NameCTIT Technical Report Series
    No.05-24
    ISSN (Print)1381-3625

    Keywords

    • EWI-737
    • CAES-EEA: Efficient Embedded Architectures
    • EC Grant Agreement nr.: FP6/001908
    • IR-54529
    • METIS-228785
    • Energy Model of Networks-on-Chip and a Bus

      Wolkotte, P. T., Smit, G. J. M., Kavaldjiev, N. K., Becker, J. E. & Becker, J., Nov 2005, Proceedings of the International Symposium on System-on-Chip (SoC 2005). Nurmi, J., Takala, J. & Hamalainen, T. D. (eds.). Piscataway, NJ, USA: IEEE, p. 82-85 4 p.

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